272 	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);  in cdv_save_display_registers()
274 	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);  in cdv_save_display_registers()
275 	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);  in cdv_save_display_registers()
277 	regs->cdv.saveDSPARB = REG_READ(DSPARB);  in cdv_save_display_registers()
278 	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);  in cdv_save_display_registers()
279 	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);  in cdv_save_display_registers()
280 	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);  in cdv_save_display_registers()
281 	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);  in cdv_save_display_registers()
282 	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);  in cdv_save_display_registers()
283 	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);  in cdv_save_display_registers()
285 	regs->cdv.saveADPA = REG_READ(ADPA);  in cdv_save_display_registers()
287 	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);  in cdv_save_display_registers()
288 	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);  in cdv_save_display_registers()
291 	regs->cdv.saveLVDS = REG_READ(LVDS);  in cdv_save_display_registers()
293 	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);  in cdv_save_display_registers()
295 	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);  in cdv_save_display_registers()
296 	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);  in cdv_save_display_registers()
297 	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);  in cdv_save_display_registers()
299 	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);  in cdv_save_display_registers()
301 	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);  in cdv_save_display_registers()
302 	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);  in cdv_save_display_registers()
325 	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);  in cdv_restore_display_registers()
327 	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);  in cdv_restore_display_registers()
328 	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);  in cdv_restore_display_registers()
348 	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);  in cdv_restore_display_registers()
349 	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);  in cdv_restore_display_registers()
350 	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);  in cdv_restore_display_registers()
351 	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);  in cdv_restore_display_registers()
352 	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);  in cdv_restore_display_registers()
353 	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);  in cdv_restore_display_registers()
355 	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);  in cdv_restore_display_registers()
356 	REG_WRITE(ADPA, regs->cdv.saveADPA);  in cdv_restore_display_registers()
359 	REG_WRITE(LVDS, regs->cdv.saveLVDS);  in cdv_restore_display_registers()
360 	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);  in cdv_restore_display_registers()
361 	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);  in cdv_restore_display_registers()
363 	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);  in cdv_restore_display_registers()
364 	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);  in cdv_restore_display_registers()
365 	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);  in cdv_restore_display_registers()
366 	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);  in cdv_restore_display_registers()
368 	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);  in cdv_restore_display_registers()
370 	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);  in cdv_restore_display_registers()
371 	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);  in cdv_restore_display_registers()