667 			      struct drm_display_mode *adjusted_mode,  in mdfld_crtc_mode_set()  argument
697 		android_hdmi_crtc_mode_set(crtc, mode, adjusted_mode,  in mdfld_crtc_mode_set()
708 		 adjusted_mode->hdisplay);  in mdfld_crtc_mode_set()
710 		 adjusted_mode->vdisplay);  in mdfld_crtc_mode_set()
712 		 adjusted_mode->hsync_start);  in mdfld_crtc_mode_set()
714 		 adjusted_mode->hsync_end);  in mdfld_crtc_mode_set()
716 		 adjusted_mode->htotal);  in mdfld_crtc_mode_set()
718 		 adjusted_mode->vsync_start);  in mdfld_crtc_mode_set()
720 		 adjusted_mode->vsync_end);  in mdfld_crtc_mode_set()
722 		 adjusted_mode->vtotal);  in mdfld_crtc_mode_set()
724 		 adjusted_mode->clock);  in mdfld_crtc_mode_set()
735 	memcpy(&gma_crtc->saved_adjusted_mode, adjusted_mode,  in mdfld_crtc_mode_set()
787 		REG_WRITE(map->size, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16)  in mdfld_crtc_mode_set()
788 				| (min(mode->crtc_hdisplay, adjusted_mode->crtc_hdisplay) - 1));  in mdfld_crtc_mode_set()
814 		offsetX = (adjusted_mode->crtc_hdisplay -  in mdfld_crtc_mode_set()
816 		offsetY = (adjusted_mode->crtc_vdisplay -  in mdfld_crtc_mode_set()
820 			((adjusted_mode->crtc_htotal - 1) << 16));  in mdfld_crtc_mode_set()
822 			((adjusted_mode->crtc_vtotal - 1) << 16));  in mdfld_crtc_mode_set()
823 		REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start -  in mdfld_crtc_mode_set()
825 			((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));  in mdfld_crtc_mode_set()
826 		REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start -  in mdfld_crtc_mode_set()
828 			((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));  in mdfld_crtc_mode_set()
829 		REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start -  in mdfld_crtc_mode_set()
831 			((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));  in mdfld_crtc_mode_set()
832 		REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start -  in mdfld_crtc_mode_set()
834 			((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));  in mdfld_crtc_mode_set()
836 		REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |  in mdfld_crtc_mode_set()
837 			((adjusted_mode->crtc_htotal - 1) << 16));  in mdfld_crtc_mode_set()
838 		REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |  in mdfld_crtc_mode_set()
839 			((adjusted_mode->crtc_vtotal - 1) << 16));  in mdfld_crtc_mode_set()
840 		REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |  in mdfld_crtc_mode_set()
841 			((adjusted_mode->crtc_hblank_end - 1) << 16));  in mdfld_crtc_mode_set()
842 		REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |  in mdfld_crtc_mode_set()
843 			((adjusted_mode->crtc_hsync_end - 1) << 16));  in mdfld_crtc_mode_set()
844 		REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |  in mdfld_crtc_mode_set()
845 			((adjusted_mode->crtc_vblank_end - 1) << 16));  in mdfld_crtc_mode_set()
846 		REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |  in mdfld_crtc_mode_set()
847 			((adjusted_mode->crtc_vsync_end - 1) << 16));  in mdfld_crtc_mode_set()
867 	clk = adjusted_mode->clock;  in mdfld_crtc_mode_set()
912 					adjusted_mode->clock, clk_tmp);  in mdfld_crtc_mode_set()