Lines Matching refs:INTEL_INFO
917 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in intel_wait_for_vblank()
988 if (INTEL_INFO(dev)->gen >= 4) { in intel_wait_for_pipe_off()
1165 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1307 if (INTEL_INFO(dev)->gen >= 4) { in assert_planes_disabled()
1343 } else if (INTEL_INFO(dev)->gen >= 7) { in assert_sprites_disabled()
1349 } else if (INTEL_INFO(dev)->gen >= 5) { in assert_sprites_disabled()
1634 BUG_ON(INTEL_INFO(dev)->gen >= 5); in i9xx_enable_pll()
1659 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_enable_pll()
1866 BUG_ON(INTEL_INFO(dev)->gen < 5); in intel_disable_shared_dpll()
2143 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); in intel_flush_primary_plane()
2211 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) in need_vtd_wa()
2240 else if (INTEL_INFO(dev)->gen >= 4) in intel_pin_and_fence_fb_obj()
2468 if (INTEL_INFO(dev)->gen >= 4) in i9xx_update_primary_plane()
2486 if (INTEL_INFO(dev)->gen < 4) { in i9xx_update_primary_plane()
2530 if (INTEL_INFO(dev)->gen >= 4 && in i9xx_update_primary_plane()
2539 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_primary_plane()
2568 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_primary_plane()
2811 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { in intel_pipe_set_base()
2814 INTEL_INFO(dev)->num_pipes); in intel_pipe_set_base()
5243 if (INTEL_INFO(dev)->num_pipes == 2) in ironlake_check_fdi_lanes()
5338 if (INTEL_INFO(dev)->gen < 4) { in intel_crtc_compute_config()
5373 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && in intel_crtc_compute_config()
5379 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { in intel_crtc_compute_config()
5664 if (INTEL_INFO(dev)->gen >= 5) { in intel_cpu_transcoder_set_m_n()
5673 if (m2_n2 && INTEL_INFO(dev)->gen < 8 && in intel_cpu_transcoder_set_m_n()
5948 if (INTEL_INFO(dev)->gen >= 4) in i9xx_update_pll()
5962 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_pll()
6036 if (INTEL_INFO(dev)->gen > 3) in intel_set_pipe_timings()
6184 if (INTEL_INFO(dev)->gen < 4 || in i9xx_set_pipeconf()
6292 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) in i9xx_get_pfit_config()
6300 if (INTEL_INFO(dev)->gen < 4) { in i9xx_get_pfit_config()
6310 if (INTEL_INFO(dev)->gen < 5) in i9xx_get_pfit_config()
6363 if (INTEL_INFO(dev)->gen >= 4) in i9xx_get_plane_config()
6373 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_plane_config()
6472 if (INTEL_INFO(dev)->gen < 4) in i9xx_get_pipe_config()
6479 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_pipe_config()
6983 if (INTEL_INFO(dev)->gen > 6) { in intel_set_pipe_csc()
7310 if (INTEL_INFO(dev)->gen >= 5) { in intel_cpu_transcoder_get_m_n()
7322 if (m2_n2 && INTEL_INFO(dev)->gen < 8 && in intel_cpu_transcoder_get_m_n()
7403 if (INTEL_INFO(dev)->gen >= 4) in ironlake_get_plane_config()
8448 if (!INTEL_INFO(dev)->cursor_needs_physical) { in intel_crtc_cursor_set_obj()
8504 if (!INTEL_INFO(dev)->cursor_needs_physical) in intel_crtc_cursor_set_obj()
9127 if (INTEL_INFO(dev)->gen >= 6) in intel_mark_idle()
9426 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) in page_flip_finished()
9727 if (INTEL_INFO(ring->dev)->gen < 5) in use_mmio_flip()
9755 if (INTEL_INFO(dev)->gen >= 4) { in intel_do_mmio_flip()
9897 if (INTEL_INFO(dev)->gen >= 4) in __intel_pageflip_stall_check()
9960 if (INTEL_INFO(dev)->gen > 3 && in intel_crtc_page_flip()
10020 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in intel_crtc_page_flip()
10030 } else if (INTEL_INFO(dev)->gen >= 7) { in intel_crtc_page_flip()
10223 if (WARN_ON(INTEL_INFO(dev)->gen > 3)) in compute_baseline_pipe_bpp()
10231 if (WARN_ON(INTEL_INFO(dev)->gen < 4)) in compute_baseline_pipe_bpp()
10242 if (WARN_ON(INTEL_INFO(dev)->gen < 4)) in compute_baseline_pipe_bpp()
10732 if (INTEL_INFO(dev)->gen < 8) { in intel_pipe_config_compare()
10770 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || in intel_pipe_config_compare()
10804 if (INTEL_INFO(dev)->gen < 4) in intel_pipe_config_compare()
10830 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) in intel_pipe_config_compare()
11964 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && in intel_primary_plane_setplane()
12022 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) in intel_primary_plane_create()
12025 if (INTEL_INFO(dev)->gen <= 3) { in intel_primary_plane_create()
12038 if (INTEL_INFO(dev)->gen >= 4) { in intel_primary_plane_create()
12183 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { in intel_crtc_init()
12512 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { in intel_framebuffer_init()
12514 } else if (INTEL_INFO(dev)->gen >= 4) { in intel_framebuffer_init()
12519 } else if (INTEL_INFO(dev)->gen >= 3) { in intel_framebuffer_init()
12551 if (INTEL_INFO(dev)->gen > 3) { in intel_framebuffer_init()
12563 if (INTEL_INFO(dev)->gen < 4) { in intel_framebuffer_init()
12573 if (INTEL_INFO(dev)->gen < 5) { in intel_framebuffer_init()
12747 switch (INTEL_INFO(dev)->gen) { in intel_init_display()
12997 if (INTEL_INFO(dev)->num_pipes == 0) in intel_modeset_init()
13027 INTEL_INFO(dev)->num_pipes, in intel_modeset_init()
13028 INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); in intel_modeset_init()
13111 if (INTEL_INFO(dev)->num_pipes == 1) in intel_check_plane_mapping()
13144 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { in intel_sanitize_crtc()
13594 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; in intel_modeset_vga_set_state()
13675 if (INTEL_INFO(dev)->num_pipes == 0) in intel_display_capture_error_state()
13698 if (INTEL_INFO(dev)->gen <= 3) { in intel_display_capture_error_state()
13702 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) in intel_display_capture_error_state()
13704 if (INTEL_INFO(dev)->gen >= 4) { in intel_display_capture_error_state()
13715 error->num_transcoders = INTEL_INFO(dev)->num_pipes; in intel_display_capture_error_state()
13755 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); in intel_display_print_error_state()
13769 if (INTEL_INFO(dev)->gen <= 3) { in intel_display_print_error_state()
13773 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) in intel_display_print_error_state()
13775 if (INTEL_INFO(dev)->gen >= 4) { in intel_display_print_error_state()