965 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)  in hsw_dp_set_ddi_pll_sel()  argument
969 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;  in hsw_dp_set_ddi_pll_sel()
972 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;  in hsw_dp_set_ddi_pll_sel()
975 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;  in hsw_dp_set_ddi_pll_sel()
982 		   struct intel_crtc_config *pipe_config, int link_bw)  in intel_dp_set_clock()  argument
1005 				pipe_config->dpll = divisor[i].dpll;  in intel_dp_set_clock()
1006 				pipe_config->clock_set = true;  in intel_dp_set_clock()
1015 			struct intel_crtc_config *pipe_config)  in intel_dp_compute_config()  argument
1019 	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;  in intel_dp_compute_config()
1035 		pipe_config->has_pch_encoder = true;  in intel_dp_compute_config()
1037 	pipe_config->has_dp_encoder = true;  in intel_dp_compute_config()
1038 	pipe_config->has_drrs = false;  in intel_dp_compute_config()
1039 	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;  in intel_dp_compute_config()
1045 			intel_gmch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1048 			intel_pch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1062 	bpp = pipe_config->pipe_bpp;  in intel_dp_compute_config()
1114 		pipe_config->limited_color_range = true;  in intel_dp_compute_config()
1118 	pipe_config->pipe_bpp = bpp;  in intel_dp_compute_config()
1119 	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);  in intel_dp_compute_config()
1123 		      pipe_config->port_clock, bpp);  in intel_dp_compute_config()
1129 			       pipe_config->port_clock,  in intel_dp_compute_config()
1130 			       &pipe_config->dp_m_n);  in intel_dp_compute_config()
1134 			pipe_config->has_drrs = true;  in intel_dp_compute_config()
1137 				pipe_config->port_clock,  in intel_dp_compute_config()
1138 				&pipe_config->dp_m2_n2);  in intel_dp_compute_config()
1142 		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);  in intel_dp_compute_config()
1144 		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);  in intel_dp_compute_config()
1870 				struct intel_crtc_config *pipe_config)  in intel_dp_get_config()  argument
1882 	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;  in intel_dp_get_config()
1907 	pipe_config->adjusted_mode.flags |= flags;  in intel_dp_get_config()
1911 		pipe_config->limited_color_range = true;  in intel_dp_get_config()
1913 	pipe_config->has_dp_encoder = true;  in intel_dp_get_config()
1915 	intel_dp_get_m_n(crtc, pipe_config);  in intel_dp_get_config()
1919 			pipe_config->port_clock = 162000;  in intel_dp_get_config()
1921 			pipe_config->port_clock = 270000;  in intel_dp_get_config()
1924 	dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in intel_dp_get_config()
1925 					    &pipe_config->dp_m_n);  in intel_dp_get_config()
1928 		ironlake_check_encoder_dotclock(pipe_config, dotclock);  in intel_dp_get_config()
1930 	pipe_config->adjusted_mode.crtc_clock = dotclock;  in intel_dp_get_config()
1933 	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {  in intel_dp_get_config()
1948 			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);  in intel_dp_get_config()
1949 		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;  in intel_dp_get_config()