562 	if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {  in intel_update_fbc()
565 	} else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {  in intel_update_fbc()
578 	if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&  in intel_update_fbc()
594 	if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&  in intel_update_fbc()
2024 	if (INTEL_INFO(dev)->gen >= 8)  in ilk_display_fifo_size()
2026 	else if (INTEL_INFO(dev)->gen >= 7)  in ilk_display_fifo_size()
2035 	if (INTEL_INFO(dev)->gen >= 8)  in ilk_plane_wm_reg_max()
2038 	else if (INTEL_INFO(dev)->gen >= 7)  in ilk_plane_wm_reg_max()
2052 	if (INTEL_INFO(dev)->gen >= 7)  in ilk_cursor_wm_reg_max()
2060 	if (INTEL_INFO(dev)->gen >= 8)  in ilk_fbc_wm_reg_max()
2081 		fifo_size /= INTEL_INFO(dev)->num_pipes;  in ilk_plane_wm_max()
2088 		if (INTEL_INFO(dev)->gen <= 6)  in ilk_plane_wm_max()
2243 	} else if (INTEL_INFO(dev)->gen >= 6) {  in intel_read_wm_latency()
2250 	} else if (INTEL_INFO(dev)->gen >= 5) {  in intel_read_wm_latency()
2263 	if (INTEL_INFO(dev)->gen == 5)  in intel_fixup_spr_wm_latency()
2270 	if (INTEL_INFO(dev)->gen == 5)  in intel_fixup_cur_wm_latency()
2283 	else if (INTEL_INFO(dev)->gen >= 6)  in ilk_wm_max_level()
2444 	if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)  in intel_compute_pipe_wm()
2529 	if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&  in ilk_wm_merge()
2534 	merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;  in ilk_wm_merge()
2622 		if (INTEL_INFO(dev)->gen >= 8)  in ilk_compute_wm_results()
2633 		if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {  in ilk_compute_wm_results()
2839 	if (INTEL_INFO(dev)->gen >= 7) {  in ilk_write_wm_values()
2891 	if (INTEL_INFO(dev)->gen >= 7 &&  in ilk_update_wm()
3000 	if (INTEL_INFO(dev)->gen >= 7) {  in ilk_wm_get_hw_state()
3362 	if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))  in gen6_rps_pm_mask()
3608 	if (INTEL_INFO(dev)->gen < 5)  in sanitize_rc6_option()
3612 	if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))  in sanitize_rc6_option()
3619 		if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))  in sanitize_rc6_option()
3633 	if (INTEL_INFO(dev)->gen == 5)  in sanitize_rc6_option()
3925 		if (INTEL_INFO(dev)->gen >= 8) {  in __gen6_update_ring_freq()
3959 	if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))  in gen6_update_ring_freq()
4650 	if (INTEL_INFO(dev)->gen != 5)  in i915_chipset_val()
4813 	if (INTEL_INFO(dev)->is_mobile)  in pvid_to_extvid()
4856 	if (INTEL_INFO(dev)->gen != 5)  in i915_update_gfx_val()
4908 	if (INTEL_INFO(dev)->gen != 5)  in i915_gfx_val()
5220 	} else if (INTEL_INFO(dev)->gen >= 6) {  in intel_disable_gt_powersave()
5271 	} else if (INTEL_INFO(dev)->gen >= 6) {  in intel_enable_gt_powersave()
7181 		if (INTEL_INFO(dev)->gen >= 7) {  in intel_init_pm()
7185 		} else if (INTEL_INFO(dev)->gen >= 5) {  in intel_init_pm()
7232 		else if (INTEL_INFO(dev)->gen == 8)  in intel_init_pm()
7274 		if (INTEL_INFO(dev)->num_pipes == 1) {  in intel_init_pm()