Lines Matching refs:cacheline_size
932 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
939 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
946 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
953 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
960 .cacheline_size = G4X_FIFO_LINE_SIZE,
967 .cacheline_size = G4X_FIFO_LINE_SIZE,
974 .cacheline_size = G4X_FIFO_LINE_SIZE,
981 .cacheline_size = G4X_FIFO_LINE_SIZE,
988 .cacheline_size = I915_FIFO_LINE_SIZE,
995 .cacheline_size = I915_FIFO_LINE_SIZE,
1002 .cacheline_size = I915_FIFO_LINE_SIZE,
1009 .cacheline_size = I830_FIFO_LINE_SIZE,
1016 .cacheline_size = I830_FIFO_LINE_SIZE,
1023 .cacheline_size = I830_FIFO_LINE_SIZE,
1060 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); in intel_calculate_wm()
1202 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; in g4x_compute_wm0()
1205 entries = DIV_ROUND_UP(entries, display->cacheline_size); in g4x_compute_wm0()
1214 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; in g4x_compute_wm0()
1217 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); in g4x_compute_wm0()
1295 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); in g4x_compute_srwm()
1300 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); in g4x_compute_srwm()
1659 i965_cursor_wm_info.cacheline_size); in i965_update_wm()
1794 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); in i9xx_update_wm()