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Lines Matching defs:i0

238 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000180 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_W()
240 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000180 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG()
260 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000230 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R()
262 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000230 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG()
292 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } in REG_MDP5_IGC()
294 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + _… in REG_MDP5_IGC_LUT()
296 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000… in REG_MDP5_IGC_LUT_REG()
319 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL()
333 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_… in REG_MDP5_CTL_LAYER()
335 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __off… in REG_MDP5_CTL_LAYER_REG()
399 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } in REG_MDP5_CTL_OP()
421 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); } in REG_MDP5_CTL_FLUSH()
444 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); } in REG_MDP5_CTL_START()
446 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); } in REG_MDP5_CTL_PACK_3D()
464 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } in REG_MDP5_PIPE()
466 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offse… in REG_MDP5_PIPE_HIST_CTL_BASE()
468 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offse… in REG_MDP5_PIPE_HIST_LUT_BASE()
470 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offse… in REG_MDP5_PIPE_HIST_LUT_SWAP()
472 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIP… in REG_MDP5_PIPE_SRC_SIZE()
486 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset… in REG_MDP5_PIPE_SRC_IMG_SIZE()
500 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(… in REG_MDP5_PIPE_SRC_XY()
514 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIP… in REG_MDP5_PIPE_OUT_SIZE()
528 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(… in REG_MDP5_PIPE_OUT_XY()
542 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PI… in REG_MDP5_PIPE_SRC0_ADDR()
544 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PI… in REG_MDP5_PIPE_SRC1_ADDR()
546 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PI… in REG_MDP5_PIPE_SRC2_ADDR()
548 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PI… in REG_MDP5_PIPE_SRC3_ADDR()
550 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset… in REG_MDP5_PIPE_SRC_STRIDE_A()
564 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset… in REG_MDP5_PIPE_SRC_STRIDE_B()
578 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __of… in REG_MDP5_PIPE_STILE_FRAME_SIZE()
580 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_P… in REG_MDP5_PIPE_SRC_FORMAT()
634 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_P… in REG_MDP5_PIPE_SRC_UNPACK()
660 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_… in REG_MDP5_PIPE_SRC_OP_MODE()
676 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __… in REG_MDP5_PIPE_SRC_CONSTANT_COLOR()
678 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset… in REG_MDP5_PIPE_FETCH_CONFIG()
680 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PI… in REG_MDP5_PIPE_VC1_RANGE()
682 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __o… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0()
684 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __o… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1()
686 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __o… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2()
688 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __… in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS()
690 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __o… in REG_MDP5_PIPE_CURRENT_SRC0_ADDR()
692 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __o… in REG_MDP5_PIPE_CURRENT_SRC1_ADDR()
694 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __o… in REG_MDP5_PIPE_CURRENT_SRC2_ADDR()
696 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __o… in REG_MDP5_PIPE_CURRENT_SRC3_ADDR()
698 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_P… in REG_MDP5_PIPE_DECIMATION()
712 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset… in REG_MDP5_PIPE_SCALE_CONFIG()
752 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __… in REG_MDP5_PIPE_SCALE_PHASE_STEP_X()
754 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __… in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y()
756 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __… in REG_MDP5_PIPE_SCALE_INIT_PHASE_X()
758 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __… in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y()
771 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } in REG_MDP5_LM()
773 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i… in REG_MDP5_LM_BLEND_COLOR_OUT()
779 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); } in REG_MDP5_LM_OUT_SIZE()
793 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0… in REG_MDP5_LM_BORDER_COLOR_0()
795 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0… in REG_MDP5_LM_BORDER_COLOR_1()
797 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_L… in REG_MDP5_LM_BLEND()
799 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __… in REG_MDP5_LM_BLEND_OP_MODE()
821 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + _… in REG_MDP5_LM_BLEND_FG_ALPHA()
823 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + _… in REG_MDP5_LM_BLEND_BG_ALPHA()
825 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000… in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0()
827 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000… in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1()
829 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000… in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0()
831 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000… in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1()
833 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000… in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0()
835 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000… in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1()
837 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000… in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0()
839 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000… in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1()
841 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i… in REG_MDP5_LM_CURSOR_IMG_SIZE()
843 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); } in REG_MDP5_LM_CURSOR_SIZE()
845 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); } in REG_MDP5_LM_CURSOR_XY()
847 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)… in REG_MDP5_LM_CURSOR_STRIDE()
849 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)… in REG_MDP5_LM_CURSOR_FORMAT()
851 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(… in REG_MDP5_LM_CURSOR_BASE_ADDR()
853 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i… in REG_MDP5_LM_CURSOR_START_XY()
855 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_… in REG_MDP5_LM_CURSOR_BLEND_CONFIG()
857 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_L… in REG_MDP5_LM_CURSOR_BLEND_PARAM()
859 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __of… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0()
861 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __of… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1()
863 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __o… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0()
865 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __o… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1()
867 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); } in REG_MDP5_LM_GC_LUT_BASE()
879 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP()
881 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP_OP_MODE()
898 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);… in REG_MDP5_DSPP_PCC_BASE()
900 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(… in REG_MDP5_DSPP_DITHER_DEPTH()
902 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP… in REG_MDP5_DSPP_HIST_CTL_BASE()
904 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP… in REG_MDP5_DSPP_HIST_LUT_BASE()
906 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP… in REG_MDP5_DSPP_HIST_LUT_SWAP()
908 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } in REG_MDP5_DSPP_PA_BASE()
910 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0… in REG_MDP5_DSPP_GAMUT_BASE()
912 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } in REG_MDP5_DSPP_GC_BASE()
925 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF()
927 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_I… in REG_MDP5_INTF_TIMING_ENGINE_EN()
929 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } in REG_MDP5_INTF_CONFIG()
931 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)… in REG_MDP5_INTF_HSYNC_CTL()
945 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_IN… in REG_MDP5_INTF_VSYNC_PERIOD_F0()
947 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_IN… in REG_MDP5_INTF_VSYNC_PERIOD_F1()
949 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(… in REG_MDP5_INTF_VSYNC_LEN_F0()
951 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(… in REG_MDP5_INTF_VSYNC_LEN_F1()
953 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_… in REG_MDP5_INTF_DISPLAY_VSTART_F0()
955 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_… in REG_MDP5_INTF_DISPLAY_VSTART_F1()
957 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_IN… in REG_MDP5_INTF_DISPLAY_VEND_F0()
959 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_IN… in REG_MDP5_INTF_DISPLAY_VEND_F1()
961 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_I… in REG_MDP5_INTF_ACTIVE_VSTART_F0()
970 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_I… in REG_MDP5_INTF_ACTIVE_VSTART_F1()
978 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INT… in REG_MDP5_INTF_ACTIVE_VEND_F0()
980 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INT… in REG_MDP5_INTF_ACTIVE_VEND_F1()
982 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(… in REG_MDP5_INTF_DISPLAY_HCTL()
996 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i… in REG_MDP5_INTF_ACTIVE_HCTL()
1011 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(… in REG_MDP5_INTF_BORDER_COLOR()
1013 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_IN… in REG_MDP5_INTF_UNDERFLOW_COLOR()
1015 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0… in REG_MDP5_INTF_HSYNC_SKEW()
1017 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(… in REG_MDP5_INTF_POLARITY_CTL()
1022 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);… in REG_MDP5_INTF_TEST_CTL()
1024 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)… in REG_MDP5_INTF_TP_COLOR0()
1026 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)… in REG_MDP5_INTF_TP_COLOR1()
1028 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __o… in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN()
1030 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(… in REG_MDP5_INTF_PANEL_FORMAT()
1032 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offse… in REG_MDP5_INTF_FRAME_LINE_COUNT_EN()
1034 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i… in REG_MDP5_INTF_FRAME_COUNT()
1036 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0… in REG_MDP5_INTF_LINE_COUNT()
1038 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_I… in REG_MDP5_INTF_DEFLICKER_CONFIG()
1040 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __off… in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF()
1042 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offs… in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF()
1044 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0… in REG_MDP5_INTF_TPG_ENABLE()
1046 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_I… in REG_MDP5_INTF_TPG_MAIN_CONTROL()
1048 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_I… in REG_MDP5_INTF_TPG_VIDEO_CONFIG()
1050 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offs… in REG_MDP5_INTF_TPG_COMPONENT_LIMITS()
1052 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF… in REG_MDP5_INTF_TPG_RECTANGLE()
1054 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_… in REG_MDP5_INTF_TPG_INITIAL_VALUE()
1056 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 +… in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME()
1058 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_IN… in REG_MDP5_INTF_TPG_RGB_MAPPING()
1068 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } in REG_MDP5_AD()
1070 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } in REG_MDP5_AD_BYPASS()
1072 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); } in REG_MDP5_AD_CTRL_0()
1074 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); } in REG_MDP5_AD_CTRL_1()
1076 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); } in REG_MDP5_AD_FRAME_SIZE()
1078 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); } in REG_MDP5_AD_CON_CTRL_0()
1080 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); } in REG_MDP5_AD_CON_CTRL_1()
1082 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); } in REG_MDP5_AD_STR_MAN()
1084 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); } in REG_MDP5_AD_VAR()
1086 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); } in REG_MDP5_AD_DITH()
1088 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); } in REG_MDP5_AD_DITH_CTRL()
1090 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); } in REG_MDP5_AD_AMP_LIM()
1092 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); } in REG_MDP5_AD_SLOPE()
1094 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); } in REG_MDP5_AD_BW_LVL()
1096 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); } in REG_MDP5_AD_LOGO_POS()
1098 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); } in REG_MDP5_AD_LUT_FI()
1100 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); } in REG_MDP5_AD_LUT_CC()
1102 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); } in REG_MDP5_AD_STR_LIM()
1104 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); } in REG_MDP5_AD_CALIB_AB()
1106 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); } in REG_MDP5_AD_CALIB_CD()
1108 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); } in REG_MDP5_AD_MODE_SEL()
1110 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); } in REG_MDP5_AD_TFILT_CTRL()
1112 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); } in REG_MDP5_AD_BL_MINMAX()
1114 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); } in REG_MDP5_AD_BL()
1116 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); } in REG_MDP5_AD_BL_MAX()
1118 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); } in REG_MDP5_AD_AL()
1120 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); } in REG_MDP5_AD_AL_MIN()
1122 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); } in REG_MDP5_AD_AL_FILT()
1124 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); } in REG_MDP5_AD_CFG_BUF()
1126 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); } in REG_MDP5_AD_LUT_AL()
1128 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); } in REG_MDP5_AD_TARG_STR()
1130 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); } in REG_MDP5_AD_START_CALC()
1132 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); } in REG_MDP5_AD_STR_OUT()
1134 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); } in REG_MDP5_AD_BL_OUT()
1136 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); } in REG_MDP5_AD_CALC_DONE()