Lines Matching refs:table
890 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits() local
896 table->FpsHighT = cpu_to_be16(tmp); in ci_init_fps_limits()
899 table->FpsLowT = cpu_to_be16(tmp); in ci_init_fps_limits()
1781 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddc_table() argument
1786 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
1787 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
1790 &table->VddcLevel[count]); in ci_populate_smc_vddc_table()
1793 table->VddcLevel[count].Smio |= in ci_populate_smc_vddc_table()
1796 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
1798 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); in ci_populate_smc_vddc_table()
1804 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddci_table() argument
1809 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
1810 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vddci_table()
1813 &table->VddciLevel[count]); in ci_populate_smc_vddci_table()
1816 table->VddciLevel[count].Smio |= in ci_populate_smc_vddci_table()
1819 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vddci_table()
1821 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); in ci_populate_smc_vddci_table()
1827 SMU7_Discrete_DpmTable *table) in ci_populate_smc_mvdd_table() argument
1832 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
1833 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
1836 &table->MvddLevel[count]); in ci_populate_smc_mvdd_table()
1839 table->MvddLevel[count].Smio |= in ci_populate_smc_mvdd_table()
1842 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
1844 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); in ci_populate_smc_mvdd_table()
1850 SMU7_Discrete_DpmTable *table) in ci_populate_smc_voltage_tables() argument
1854 ret = ci_populate_smc_vddc_table(rdev, table); in ci_populate_smc_voltage_tables()
1858 ret = ci_populate_smc_vddci_table(rdev, table); in ci_populate_smc_voltage_tables()
1862 ret = ci_populate_smc_mvdd_table(rdev, table); in ci_populate_smc_voltage_tables()
2160 SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
2167 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2169 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2171 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2172 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2173 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()
2182 SMU7_Discrete_DpmTable *table) in ci_populate_smc_uvd_level() argument
2188 table->UvdLevelCount = in ci_populate_smc_uvd_level()
2191 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
2192 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
2194 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
2196 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
2198 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2202 table->UvdLevel[count].VclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2206 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2210 table->UvdLevel[count].DclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2214 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2216 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
2217 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
2218 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); in ci_populate_smc_uvd_level()
2225 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vce_level() argument
2231 table->VceLevelCount = in ci_populate_smc_vce_level()
2234 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
2235 table->VceLevel[count].Frequency = in ci_populate_smc_vce_level()
2237 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
2239 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
2243 table->VceLevel[count].Frequency, false, ÷rs); in ci_populate_smc_vce_level()
2247 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2249 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
2250 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
2258 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acp_level() argument
2264 table->AcpLevelCount = (u8) in ci_populate_smc_acp_level()
2267 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
2268 table->AcpLevel[count].Frequency = in ci_populate_smc_acp_level()
2270 table->AcpLevel[count].MinVoltage = in ci_populate_smc_acp_level()
2272 table->AcpLevel[count].MinPhases = 1; in ci_populate_smc_acp_level()
2276 table->AcpLevel[count].Frequency, false, ÷rs); in ci_populate_smc_acp_level()
2280 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2282 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); in ci_populate_smc_acp_level()
2283 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); in ci_populate_smc_acp_level()
2290 SMU7_Discrete_DpmTable *table) in ci_populate_smc_samu_level() argument
2296 table->SamuLevelCount = in ci_populate_smc_samu_level()
2299 for (count = 0; count < table->SamuLevelCount; count++) { in ci_populate_smc_samu_level()
2300 table->SamuLevel[count].Frequency = in ci_populate_smc_samu_level()
2302 table->SamuLevel[count].MinVoltage = in ci_populate_smc_samu_level()
2304 table->SamuLevel[count].MinPhases = 1; in ci_populate_smc_samu_level()
2308 table->SamuLevel[count].Frequency, false, ÷rs); in ci_populate_smc_samu_level()
2312 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2314 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); in ci_populate_smc_samu_level()
2315 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); in ci_populate_smc_samu_level()
2524 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acpi_level() argument
2535 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; in ci_populate_smc_acpi_level()
2538 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2540 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2542 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2544 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
2548 table->ACPILevel.SclkFrequency, false, ÷rs); in ci_populate_smc_acpi_level()
2552 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
2553 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_smc_acpi_level()
2554 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
2562 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; in ci_populate_smc_acpi_level()
2563 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; in ci_populate_smc_acpi_level()
2564 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
2565 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
2566 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
2567 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
2568 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
2569 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
2571 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); in ci_populate_smc_acpi_level()
2572 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); in ci_populate_smc_acpi_level()
2573 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); in ci_populate_smc_acpi_level()
2574 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); in ci_populate_smc_acpi_level()
2575 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); in ci_populate_smc_acpi_level()
2576 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); in ci_populate_smc_acpi_level()
2577 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); in ci_populate_smc_acpi_level()
2578 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); in ci_populate_smc_acpi_level()
2579 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); in ci_populate_smc_acpi_level()
2580 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); in ci_populate_smc_acpi_level()
2581 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); in ci_populate_smc_acpi_level()
2583 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; in ci_populate_smc_acpi_level()
2584 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
2588 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
2591 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
2596 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
2598 table->MemoryACPILevel.MinMvdd = in ci_populate_smc_acpi_level()
2606 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); in ci_populate_smc_acpi_level()
2607 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); in ci_populate_smc_acpi_level()
2608 table->MemoryACPILevel.MpllAdFuncCntl = in ci_populate_smc_acpi_level()
2610 table->MemoryACPILevel.MpllDqFuncCntl = in ci_populate_smc_acpi_level()
2612 table->MemoryACPILevel.MpllFuncCntl = in ci_populate_smc_acpi_level()
2614 table->MemoryACPILevel.MpllFuncCntl_1 = in ci_populate_smc_acpi_level()
2616 table->MemoryACPILevel.MpllFuncCntl_2 = in ci_populate_smc_acpi_level()
2618 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
2619 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
2621 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
2622 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
2623 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
2624 table->MemoryACPILevel.DownH = 100; in ci_populate_smc_acpi_level()
2625 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
2626 table->MemoryACPILevel.ActivityLevel = in ci_populate_smc_acpi_level()
2629 table->MemoryACPILevel.StutterEnable = false; in ci_populate_smc_acpi_level()
2630 table->MemoryACPILevel.StrobeEnable = false; in ci_populate_smc_acpi_level()
2631 table->MemoryACPILevel.EdcReadEnable = false; in ci_populate_smc_acpi_level()
2632 table->MemoryACPILevel.EdcWriteEnable = false; in ci_populate_smc_acpi_level()
2633 table->MemoryACPILevel.RttEnable = false; in ci_populate_smc_acpi_level()
3054 static int ci_find_boot_level(struct ci_single_dpm_table *table, in ci_find_boot_level() argument
3060 for(i = 0; i < table->count; i++) { in ci_find_boot_level()
3061 if (value == table->dpm_levels[i].value) { in ci_find_boot_level()
3075 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table() local
3083 ci_populate_smc_voltage_tables(rdev, table); in ci_init_smc_table()
3088 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ci_init_smc_table()
3091 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ci_init_smc_table()
3094 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ci_init_smc_table()
3111 ci_populate_smc_link_level(rdev, table); in ci_init_smc_table()
3113 ret = ci_populate_smc_acpi_level(rdev, table); in ci_init_smc_table()
3117 ret = ci_populate_smc_vce_level(rdev, table); in ci_init_smc_table()
3121 ret = ci_populate_smc_acp_level(rdev, table); in ci_init_smc_table()
3125 ret = ci_populate_smc_samu_level(rdev, table); in ci_init_smc_table()
3133 ret = ci_populate_smc_uvd_level(rdev, table); in ci_init_smc_table()
3137 table->UvdBootLevel = 0; in ci_init_smc_table()
3138 table->VceBootLevel = 0; in ci_init_smc_table()
3139 table->AcpBootLevel = 0; in ci_init_smc_table()
3140 table->SamuBootLevel = 0; in ci_init_smc_table()
3141 table->GraphicsBootLevel = 0; in ci_init_smc_table()
3142 table->MemoryBootLevel = 0; in ci_init_smc_table()
3152 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3153 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3154 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3162 table->UVDInterval = 1; in ci_init_smc_table()
3163 table->VCEInterval = 1; in ci_init_smc_table()
3164 table->ACPInterval = 1; in ci_init_smc_table()
3165 table->SAMUInterval = 1; in ci_init_smc_table()
3166 table->GraphicsVoltageChangeEnable = 1; in ci_init_smc_table()
3167 table->GraphicsThermThrottleEnable = 1; in ci_init_smc_table()
3168 table->GraphicsInterval = 1; in ci_init_smc_table()
3169 table->VoltageInterval = 1; in ci_init_smc_table()
3170 table->ThermalInterval = 1; in ci_init_smc_table()
3171 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3173 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3175 table->MemoryVoltageChangeEnable = 1; in ci_init_smc_table()
3176 table->MemoryInterval = 1; in ci_init_smc_table()
3177 table->VoltageResponseTime = 0; in ci_init_smc_table()
3178 table->VddcVddciDelta = 4000; in ci_init_smc_table()
3179 table->PhaseResponseTime = 0; in ci_init_smc_table()
3180 table->MemoryThermThrottleEnable = 1; in ci_init_smc_table()
3181 table->PCIeBootLinkLevel = 0; in ci_init_smc_table()
3182 table->PCIeGenInterval = 1; in ci_init_smc_table()
3184 table->SVI2Enable = 1; in ci_init_smc_table()
3186 table->SVI2Enable = 0; in ci_init_smc_table()
3188 table->ThermGpio = 17; in ci_init_smc_table()
3189 table->SclkStepSize = 0x4000; in ci_init_smc_table()
3191 table->SystemFlags = cpu_to_be32(table->SystemFlags); in ci_init_smc_table()
3192 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); in ci_init_smc_table()
3193 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); in ci_init_smc_table()
3194 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); in ci_init_smc_table()
3195 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); in ci_init_smc_table()
3196 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); in ci_init_smc_table()
3197 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); in ci_init_smc_table()
3198 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); in ci_init_smc_table()
3199 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); in ci_init_smc_table()
3200 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); in ci_init_smc_table()
3201 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); in ci_init_smc_table()
3202 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); in ci_init_smc_table()
3203 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); in ci_init_smc_table()
3204 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); in ci_init_smc_table()
3209 (u8 *)&table->SystemFlags, in ci_init_smc_table()
3615 struct radeon_vce_clock_voltage_dependency_table *table = in ci_get_vce_boot_level() local
3618 for (i = 0; i < table->count; i++) { in ci_get_vce_boot_level()
3619 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
3623 return table->count - 1; in ci_get_vce_boot_level()
3854 struct ci_mc_reg_table *table) in ci_set_mc_special_registers() argument
3860 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
3863 switch(table->mc_reg_address[i].s1 << 2) { in ci_set_mc_special_registers()
3866 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ci_set_mc_special_registers()
3867 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ci_set_mc_special_registers()
3868 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
3869 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
3870 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
3877 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ci_set_mc_special_registers()
3878 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ci_set_mc_special_registers()
3879 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
3880 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
3881 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
3883 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
3890 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
3891 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
3892 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
3893 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
3894 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
3903 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ci_set_mc_special_registers()
3904 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ci_set_mc_special_registers()
3905 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
3906 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
3907 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
3919 table->last = j; in ci_set_mc_special_registers()
3997 static void ci_set_valid_flag(struct ci_mc_reg_table *table) in ci_set_valid_flag() argument
4001 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
4002 for (j = 1; j < table->num_entries; j++) { in ci_set_valid_flag()
4003 if (table->mc_reg_table_entry[j-1].mc_data[i] != in ci_set_valid_flag()
4004 table->mc_reg_table_entry[j].mc_data[i]) { in ci_set_valid_flag()
4005 table->valid_flag |= 1 << i; in ci_set_valid_flag()
4012 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) in ci_set_s0_mc_reg_index() argument
4017 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
4018 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()
4019 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ci_set_s0_mc_reg_index()
4020 address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index()
4024 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, in ci_copy_vbios_mc_reg_table() argument
4029 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_copy_vbios_mc_reg_table()
4031 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in ci_copy_vbios_mc_reg_table()
4034 for (i = 0; i < table->last; i++) in ci_copy_vbios_mc_reg_table()
4035 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_mc_reg_table()
4037 ci_table->last = table->last; in ci_copy_vbios_mc_reg_table()
4039 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_mc_reg_table()
4041 table->mc_reg_table_entry[i].mclk_max; in ci_copy_vbios_mc_reg_table()
4042 for (j = 0; j < table->last; j++) in ci_copy_vbios_mc_reg_table()
4044 table->mc_reg_table_entry[i].mc_data[j]; in ci_copy_vbios_mc_reg_table()
4046 ci_table->num_entries = table->num_entries; in ci_copy_vbios_mc_reg_table()
4054 struct atom_mc_reg_table *table; in ci_initialize_mc_reg_table() local
4059 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); in ci_initialize_mc_reg_table()
4060 if (!table) in ci_initialize_mc_reg_table()
4084 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in ci_initialize_mc_reg_table()
4088 ret = ci_copy_vbios_mc_reg_table(table, ci_table); in ci_initialize_mc_reg_table()
4101 kfree(table); in ci_initialize_mc_reg_table()
4410 struct radeon_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage() argument
4414 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4415 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4416 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4421 struct radeon_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage() argument
4425 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4426 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4427 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4432 struct radeon_vce_clock_voltage_dependency_table *table) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage() argument
4436 if (table) { in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4437 for (i = 0; i < table->count; i++) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4438 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4443 struct radeon_uvd_clock_voltage_dependency_table *table) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage() argument
4447 if (table) { in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4448 for (i = 0; i < table->count; i++) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4449 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4454 struct radeon_phase_shedding_limits_table *table) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage() argument
4458 if (table) { in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
4459 for (i = 0; i < table->count; i++) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
4460 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
4465 struct radeon_clock_and_voltage_limits *table) in ci_patch_clock_voltage_limits_with_vddc_leakage() argument
4467 if (table) { in ci_patch_clock_voltage_limits_with_vddc_leakage()
4468 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
4469 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); in ci_patch_clock_voltage_limits_with_vddc_leakage()
4474 struct radeon_cac_leakage_table *table) in ci_patch_cac_leakage_table_with_vddc_leakage() argument
4478 if (table) { in ci_patch_cac_leakage_table_with_vddc_leakage()
4479 for (i = 0; i < table->count; i++) in ci_patch_cac_leakage_table_with_vddc_leakage()
4480 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); in ci_patch_cac_leakage_table_with_vddc_leakage()