Lines Matching refs:dev_priv
102 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) in r600_do_wait_for_fifo() argument
106 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
108 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
110 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
127 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) in r600_do_wait_for_idle() argument
131 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
133 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
134 ret = r600_do_wait_for_fifo(dev_priv, 8); in r600_do_wait_for_idle()
136 ret = r600_do_wait_for_fifo(dev_priv, 16); in r600_do_wait_for_idle()
139 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
180 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_page_table_init() local
181 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; in r600_page_table_init()
234 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_vm_flush_gart_range() local
236 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_flush_gart_range()
237 …RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_si… in r600_vm_flush_gart_range()
249 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_vm_init() local
255 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
256 …RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r600_vm_init()
305 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); in r600_vm_init()
306 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
307 …RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r600_vm_init()
312 static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) in r600_cp_init_microcode() argument
327 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_cp_init_microcode()
343 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { in r600_cp_init_microcode()
354 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); in r600_cp_init_microcode()
357 if (dev_priv->pfp_fw->size != pfp_req_size) { in r600_cp_init_microcode()
360 dev_priv->pfp_fw->size, fw_name); in r600_cp_init_microcode()
366 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); in r600_cp_init_microcode()
369 if (dev_priv->me_fw->size != me_req_size) { in r600_cp_init_microcode()
372 dev_priv->me_fw->size, fw_name); in r600_cp_init_microcode()
383 release_firmware(dev_priv->pfp_fw); in r600_cp_init_microcode()
384 dev_priv->pfp_fw = NULL; in r600_cp_init_microcode()
385 release_firmware(dev_priv->me_fw); in r600_cp_init_microcode()
386 dev_priv->me_fw = NULL; in r600_cp_init_microcode()
391 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) in r600_cp_load_microcode() argument
396 if (!dev_priv->me_fw || !dev_priv->pfp_fw) in r600_cp_load_microcode()
399 r600_do_cp_stop(dev_priv); in r600_cp_load_microcode()
414 fw_data = (const __be32 *)dev_priv->me_fw->data; in r600_cp_load_microcode()
420 fw_data = (const __be32 *)dev_priv->pfp_fw->data; in r600_cp_load_microcode()
434 drm_radeon_private_t *dev_priv = dev->dev_private; in r700_vm_init() local
440 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r700_vm_init()
441 …RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r700_vm_init()
477 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); in r700_vm_init()
478 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); in r700_vm_init()
479 …RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r700_vm_init()
484 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) in r700_cp_load_microcode() argument
489 if (!dev_priv->me_fw || !dev_priv->pfp_fw) in r700_cp_load_microcode()
492 r600_do_cp_stop(dev_priv); in r700_cp_load_microcode()
507 fw_data = (const __be32 *)dev_priv->pfp_fw->data; in r700_cp_load_microcode()
513 fw_data = (const __be32 *)dev_priv->me_fw->data; in r700_cp_load_microcode()
525 static void r600_test_writeback(drm_radeon_private_t *dev_priv) in r600_test_writeback() argument
530 dev_priv->writeback_works = 0; in r600_test_writeback()
535 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); in r600_test_writeback()
539 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { in r600_test_writeback()
542 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); in r600_test_writeback()
548 if (tmp < dev_priv->usec_timeout) { in r600_test_writeback()
549 dev_priv->writeback_works = 1; in r600_test_writeback()
552 dev_priv->writeback_works = 0; in r600_test_writeback()
556 dev_priv->writeback_works = 0; in r600_test_writeback()
560 if (!dev_priv->writeback_works) { in r600_test_writeback()
574 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_engine_reset() local
603 r600_do_cp_reset(dev_priv); in r600_do_engine_reset()
606 dev_priv->cp_running = 0; in r600_do_engine_reset()
730 drm_radeon_private_t *dev_priv) in r600_gfx_init() argument
754 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
756 dev_priv->r600_max_pipes = 4; in r600_gfx_init()
757 dev_priv->r600_max_tile_pipes = 8; in r600_gfx_init()
758 dev_priv->r600_max_simds = 4; in r600_gfx_init()
759 dev_priv->r600_max_backends = 4; in r600_gfx_init()
760 dev_priv->r600_max_gprs = 256; in r600_gfx_init()
761 dev_priv->r600_max_threads = 192; in r600_gfx_init()
762 dev_priv->r600_max_stack_entries = 256; in r600_gfx_init()
763 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
764 dev_priv->r600_max_gs_threads = 16; in r600_gfx_init()
765 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
766 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
767 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
768 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
772 dev_priv->r600_max_pipes = 2; in r600_gfx_init()
773 dev_priv->r600_max_tile_pipes = 2; in r600_gfx_init()
774 dev_priv->r600_max_simds = 3; in r600_gfx_init()
775 dev_priv->r600_max_backends = 1; in r600_gfx_init()
776 dev_priv->r600_max_gprs = 128; in r600_gfx_init()
777 dev_priv->r600_max_threads = 192; in r600_gfx_init()
778 dev_priv->r600_max_stack_entries = 128; in r600_gfx_init()
779 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
780 dev_priv->r600_max_gs_threads = 4; in r600_gfx_init()
781 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
782 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
783 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
784 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
790 dev_priv->r600_max_pipes = 1; in r600_gfx_init()
791 dev_priv->r600_max_tile_pipes = 1; in r600_gfx_init()
792 dev_priv->r600_max_simds = 2; in r600_gfx_init()
793 dev_priv->r600_max_backends = 1; in r600_gfx_init()
794 dev_priv->r600_max_gprs = 128; in r600_gfx_init()
795 dev_priv->r600_max_threads = 192; in r600_gfx_init()
796 dev_priv->r600_max_stack_entries = 128; in r600_gfx_init()
797 dev_priv->r600_max_hw_contexts = 4; in r600_gfx_init()
798 dev_priv->r600_max_gs_threads = 4; in r600_gfx_init()
799 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
800 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
801 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
802 dev_priv->r600_sq_num_cf_insts = 1; in r600_gfx_init()
805 dev_priv->r600_max_pipes = 4; in r600_gfx_init()
806 dev_priv->r600_max_tile_pipes = 4; in r600_gfx_init()
807 dev_priv->r600_max_simds = 4; in r600_gfx_init()
808 dev_priv->r600_max_backends = 4; in r600_gfx_init()
809 dev_priv->r600_max_gprs = 192; in r600_gfx_init()
810 dev_priv->r600_max_threads = 192; in r600_gfx_init()
811 dev_priv->r600_max_stack_entries = 256; in r600_gfx_init()
812 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
813 dev_priv->r600_max_gs_threads = 16; in r600_gfx_init()
814 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
815 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
816 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
817 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
839 switch (dev_priv->r600_max_tile_pipes) { in r600_gfx_init()
874 …R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_M… in r600_gfx_init()
878 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); in r600_gfx_init()
880 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); in r600_gfx_init()
882 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, in r600_gfx_init()
893 dev_priv->r600_group_size = 512; in r600_gfx_init()
895 dev_priv->r600_group_size = 256; in r600_gfx_init()
897 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); in r600_gfx_init()
899 dev_priv->r600_nbanks = 8; in r600_gfx_init()
901 dev_priv->r600_nbanks = 4; in r600_gfx_init()
925 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) in r600_gfx_init()
930 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) in r600_gfx_init()
934 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || in r600_gfx_init()
935 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || in r600_gfx_init()
936 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
937 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
938 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
939 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) in r600_gfx_init()
955 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
956 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
957 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
958 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { in r600_gfx_init()
963 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || in r600_gfx_init()
964 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { in r600_gfx_init()
985 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { in r600_gfx_init()
999 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
1000 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
1001 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
1002 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { in r600_gfx_init()
1019 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || in r600_gfx_init()
1020 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { in r600_gfx_init()
1034 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { in r600_gfx_init()
1057 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
1058 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
1059 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
1060 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) in r600_gfx_init()
1095 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
1114 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; in r600_gfx_init()
1146 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
1181 static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv, in r700_get_tile_pipe_to_backend_map() argument
1223 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_get_tile_pipe_to_backend_map()
1356 drm_radeon_private_t *dev_priv) in r700_gfx_init() argument
1379 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1381 dev_priv->r600_max_pipes = 4; in r700_gfx_init()
1382 dev_priv->r600_max_tile_pipes = 8; in r700_gfx_init()
1383 dev_priv->r600_max_simds = 10; in r700_gfx_init()
1384 dev_priv->r600_max_backends = 4; in r700_gfx_init()
1385 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1386 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1387 dev_priv->r600_max_stack_entries = 512; in r700_gfx_init()
1388 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1389 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1390 dev_priv->r600_sx_max_export_size = 128; in r700_gfx_init()
1391 dev_priv->r600_sx_max_export_pos_size = 16; in r700_gfx_init()
1392 dev_priv->r600_sx_max_export_smx_size = 112; in r700_gfx_init()
1393 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1395 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1396 dev_priv->r700_sc_prim_fifo_size = 0xF9; in r700_gfx_init()
1397 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1398 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1401 dev_priv->r600_max_pipes = 2; in r700_gfx_init()
1402 dev_priv->r600_max_tile_pipes = 4; in r700_gfx_init()
1403 dev_priv->r600_max_simds = 8; in r700_gfx_init()
1404 dev_priv->r600_max_backends = 2; in r700_gfx_init()
1405 dev_priv->r600_max_gprs = 128; in r700_gfx_init()
1406 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1407 dev_priv->r600_max_stack_entries = 256; in r700_gfx_init()
1408 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1409 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1410 dev_priv->r600_sx_max_export_size = 256; in r700_gfx_init()
1411 dev_priv->r600_sx_max_export_pos_size = 32; in r700_gfx_init()
1412 dev_priv->r600_sx_max_export_smx_size = 224; in r700_gfx_init()
1413 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1415 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1416 dev_priv->r700_sc_prim_fifo_size = 0xf9; in r700_gfx_init()
1417 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1418 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1419 if (dev_priv->r600_sx_max_export_pos_size > 16) { in r700_gfx_init()
1420 dev_priv->r600_sx_max_export_pos_size -= 16; in r700_gfx_init()
1421 dev_priv->r600_sx_max_export_smx_size += 16; in r700_gfx_init()
1425 dev_priv->r600_max_pipes = 2; in r700_gfx_init()
1426 dev_priv->r600_max_tile_pipes = 2; in r700_gfx_init()
1427 dev_priv->r600_max_simds = 2; in r700_gfx_init()
1428 dev_priv->r600_max_backends = 1; in r700_gfx_init()
1429 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1430 dev_priv->r600_max_threads = 192; in r700_gfx_init()
1431 dev_priv->r600_max_stack_entries = 256; in r700_gfx_init()
1432 dev_priv->r600_max_hw_contexts = 4; in r700_gfx_init()
1433 dev_priv->r600_max_gs_threads = 8 * 2; in r700_gfx_init()
1434 dev_priv->r600_sx_max_export_size = 128; in r700_gfx_init()
1435 dev_priv->r600_sx_max_export_pos_size = 16; in r700_gfx_init()
1436 dev_priv->r600_sx_max_export_smx_size = 112; in r700_gfx_init()
1437 dev_priv->r600_sq_num_cf_insts = 1; in r700_gfx_init()
1439 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1440 dev_priv->r700_sc_prim_fifo_size = 0x40; in r700_gfx_init()
1441 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1442 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1445 dev_priv->r600_max_pipes = 4; in r700_gfx_init()
1446 dev_priv->r600_max_tile_pipes = 4; in r700_gfx_init()
1447 dev_priv->r600_max_simds = 8; in r700_gfx_init()
1448 dev_priv->r600_max_backends = 4; in r700_gfx_init()
1449 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1450 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1451 dev_priv->r600_max_stack_entries = 512; in r700_gfx_init()
1452 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1453 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1454 dev_priv->r600_sx_max_export_size = 256; in r700_gfx_init()
1455 dev_priv->r600_sx_max_export_pos_size = 32; in r700_gfx_init()
1456 dev_priv->r600_sx_max_export_smx_size = 224; in r700_gfx_init()
1457 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1459 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1460 dev_priv->r700_sc_prim_fifo_size = 0x100; in r700_gfx_init()
1461 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1462 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1464 if (dev_priv->r600_sx_max_export_pos_size > 16) { in r700_gfx_init()
1465 dev_priv->r600_sx_max_export_pos_size -= 16; in r700_gfx_init()
1466 dev_priv->r600_sx_max_export_smx_size += 16; in r700_gfx_init()
1489 switch (dev_priv->r600_max_tile_pipes) { in r700_gfx_init()
1506 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) in r700_gfx_init()
1527 …R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_M… in r700_gfx_init()
1531 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); in r700_gfx_init()
1533 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); in r700_gfx_init()
1535 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) in r700_gfx_init()
1538 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv, in r700_gfx_init()
1539 dev_priv->r600_max_tile_pipes, in r700_gfx_init()
1550 dev_priv->r600_group_size = 512; in r700_gfx_init()
1552 dev_priv->r600_group_size = 256; in r700_gfx_init()
1554 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); in r700_gfx_init()
1556 dev_priv->r600_nbanks = 8; in r700_gfx_init()
1558 dev_priv->r600_nbanks = 4; in r700_gfx_init()
1591 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); in r700_gfx_init()
1594 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) in r700_gfx_init()
1602 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1615 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { in r700_gfx_init()
1621 …RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_si… in r700_gfx_init()
1622 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | in r700_gfx_init()
1623 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); in r700_gfx_init()
1625 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | in r700_gfx_init()
1626 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | in r700_gfx_init()
1627 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); in r700_gfx_init()
1639 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | in r700_gfx_init()
1642 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1670 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) in r700_gfx_init()
1676 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | in r700_gfx_init()
1677 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | in r700_gfx_init()
1678 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); in r700_gfx_init()
1680 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | in r700_gfx_init()
1681 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); in r700_gfx_init()
1683 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | in r700_gfx_init()
1684 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | in r700_gfx_init()
1685 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); in r700_gfx_init()
1686 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) in r700_gfx_init()
1687 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); in r700_gfx_init()
1689 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); in r700_gfx_init()
1692 …RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_e… in r700_gfx_init()
1693 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); in r700_gfx_init()
1695 …RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_e… in r700_gfx_init()
1696 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); in r700_gfx_init()
1698 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1699 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1700 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1701 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); in r700_gfx_init()
1715 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) in r700_gfx_init()
1722 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1735 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; in r700_gfx_init()
1782 drm_radeon_private_t *dev_priv, in r600_cp_init_ring_buffer() argument
1789 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_cp_init_ring_buffer()
1790 r700_gfx_init(dev, dev_priv); in r600_cp_init_ring_buffer()
1792 r600_gfx_init(dev, dev_priv); in r600_cp_init_ring_buffer()
1805 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1806 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1810 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1811 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1824 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1825 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1830 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1831 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1837 SET_RING_HEAD(dev_priv, 0); in r600_cp_init_ring_buffer()
1838 dev_priv->ring.tail = 0; in r600_cp_init_ring_buffer()
1841 if (dev_priv->flags & RADEON_IS_AGP) { in r600_cp_init_ring_buffer()
1842 rptr_addr = dev_priv->ring_rptr->offset in r600_cp_init_ring_buffer()
1844 dev_priv->gart_vm_start; in r600_cp_init_ring_buffer()
1848 rptr_addr = dev_priv->ring_rptr->offset in r600_cp_init_ring_buffer()
1850 + dev_priv->gart_vm_start; in r600_cp_init_ring_buffer()
1858 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1859 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1862 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1863 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1867 if (dev_priv->flags & RADEON_IS_AGP) { in r600_cp_init_ring_buffer()
1869 radeon_write_agp_base(dev_priv, dev->agp->base); in r600_cp_init_ring_buffer()
1872 radeon_write_agp_location(dev_priv, in r600_cp_init_ring_buffer()
1873 (((dev_priv->gart_vm_start - 1 + in r600_cp_init_ring_buffer()
1874 dev_priv->gart_size) & 0xffff0000) | in r600_cp_init_ring_buffer()
1875 (dev_priv->gart_vm_start >> 16))); in r600_cp_init_ring_buffer()
1877 ring_start = (dev_priv->cp_ring->offset in r600_cp_init_ring_buffer()
1879 + dev_priv->gart_vm_start); in r600_cp_init_ring_buffer()
1882 ring_start = (dev_priv->cp_ring->offset in r600_cp_init_ring_buffer()
1884 + dev_priv->gart_vm_start); in r600_cp_init_ring_buffer()
1914 radeon_enable_bm(dev_priv); in r600_cp_init_ring_buffer()
1916 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); in r600_cp_init_ring_buffer()
1919 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); in r600_cp_init_ring_buffer()
1922 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); in r600_cp_init_ring_buffer()
1933 r600_do_wait_for_idle(dev_priv); in r600_cp_init_ring_buffer()
1939 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_cleanup_cp() local
1950 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_cleanup_cp()
1951 if (dev_priv->cp_ring != NULL) { in r600_do_cleanup_cp()
1952 drm_legacy_ioremapfree(dev_priv->cp_ring, dev); in r600_do_cleanup_cp()
1953 dev_priv->cp_ring = NULL; in r600_do_cleanup_cp()
1955 if (dev_priv->ring_rptr != NULL) { in r600_do_cleanup_cp()
1956 drm_legacy_ioremapfree(dev_priv->ring_rptr, dev); in r600_do_cleanup_cp()
1957 dev_priv->ring_rptr = NULL; in r600_do_cleanup_cp()
1967 if (dev_priv->gart_info.bus_addr) in r600_do_cleanup_cp()
1968 r600_page_table_cleanup(dev, &dev_priv->gart_info); in r600_do_cleanup_cp()
1970 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { in r600_do_cleanup_cp()
1971 drm_legacy_ioremapfree(&dev_priv->gart_info.mapping, dev); in r600_do_cleanup_cp()
1972 dev_priv->gart_info.addr = NULL; in r600_do_cleanup_cp()
1976 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); in r600_do_cleanup_cp()
1984 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_init_cp() local
1989 mutex_init(&dev_priv->cs_mutex); in r600_do_init_cp()
1992 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { in r600_do_init_cp()
1998 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { in r600_do_init_cp()
2000 dev_priv->flags &= ~RADEON_IS_AGP; in r600_do_init_cp()
2005 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) in r600_do_init_cp()
2008 dev_priv->flags |= RADEON_IS_AGP; in r600_do_init_cp()
2011 dev_priv->usec_timeout = init->usec_timeout; in r600_do_init_cp()
2012 if (dev_priv->usec_timeout < 1 || in r600_do_init_cp()
2013 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { in r600_do_init_cp()
2021 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; in r600_do_init_cp()
2022 dev_priv->do_boxes = 0; in r600_do_init_cp()
2023 dev_priv->cp_mode = init->cp_mode; in r600_do_init_cp()
2038 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; in r600_do_init_cp()
2042 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; in r600_do_init_cp()
2045 dev_priv->front_offset = init->front_offset; in r600_do_init_cp()
2046 dev_priv->front_pitch = init->front_pitch; in r600_do_init_cp()
2047 dev_priv->back_offset = init->back_offset; in r600_do_init_cp()
2048 dev_priv->back_pitch = init->back_pitch; in r600_do_init_cp()
2050 dev_priv->ring_offset = init->ring_offset; in r600_do_init_cp()
2051 dev_priv->ring_rptr_offset = init->ring_rptr_offset; in r600_do_init_cp()
2052 dev_priv->buffers_offset = init->buffers_offset; in r600_do_init_cp()
2053 dev_priv->gart_textures_offset = init->gart_textures_offset; in r600_do_init_cp()
2062 dev_priv->cp_ring = drm_legacy_findmap(dev, init->ring_offset); in r600_do_init_cp()
2063 if (!dev_priv->cp_ring) { in r600_do_init_cp()
2068 dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset); in r600_do_init_cp()
2069 if (!dev_priv->ring_rptr) { in r600_do_init_cp()
2083 dev_priv->gart_textures = in r600_do_init_cp()
2085 if (!dev_priv->gart_textures) { in r600_do_init_cp()
2094 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
2095 drm_legacy_ioremap_wc(dev_priv->cp_ring, dev); in r600_do_init_cp()
2096 drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev); in r600_do_init_cp()
2098 if (!dev_priv->cp_ring->handle || in r600_do_init_cp()
2099 !dev_priv->ring_rptr->handle || in r600_do_init_cp()
2108 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; in r600_do_init_cp()
2109 dev_priv->ring_rptr->handle = in r600_do_init_cp()
2110 (void *)(unsigned long)dev_priv->ring_rptr->offset; in r600_do_init_cp()
2115 dev_priv->cp_ring->handle); in r600_do_init_cp()
2117 dev_priv->ring_rptr->handle); in r600_do_init_cp()
2122 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; in r600_do_init_cp()
2123 dev_priv->fb_size = in r600_do_init_cp()
2124 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) in r600_do_init_cp()
2125 - dev_priv->fb_location; in r600_do_init_cp()
2127 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | in r600_do_init_cp()
2128 ((dev_priv->front_offset in r600_do_init_cp()
2129 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
2131 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | in r600_do_init_cp()
2132 ((dev_priv->back_offset in r600_do_init_cp()
2133 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
2135 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | in r600_do_init_cp()
2136 ((dev_priv->depth_offset in r600_do_init_cp()
2137 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
2139 dev_priv->gart_size = init->gart_size; in r600_do_init_cp()
2142 if (dev_priv->new_memmap) { in r600_do_init_cp()
2153 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
2156 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && in r600_do_init_cp()
2157 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { in r600_do_init_cp()
2166 base = dev_priv->fb_location + dev_priv->fb_size; in r600_do_init_cp()
2167 if (base < dev_priv->fb_location || in r600_do_init_cp()
2168 ((base + dev_priv->gart_size) & 0xfffffffful) < base) in r600_do_init_cp()
2169 base = dev_priv->fb_location in r600_do_init_cp()
2170 - dev_priv->gart_size; in r600_do_init_cp()
2172 dev_priv->gart_vm_start = base & 0xffc00000u; in r600_do_init_cp()
2173 if (dev_priv->gart_vm_start != base) in r600_do_init_cp()
2175 base, dev_priv->gart_vm_start); in r600_do_init_cp()
2180 if (dev_priv->flags & RADEON_IS_AGP) in r600_do_init_cp()
2181 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset in r600_do_init_cp()
2183 + dev_priv->gart_vm_start); in r600_do_init_cp()
2186 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset in r600_do_init_cp()
2188 + dev_priv->gart_vm_start); in r600_do_init_cp()
2191 (unsigned int) dev_priv->fb_location, in r600_do_init_cp()
2192 (unsigned int) dev_priv->fb_size); in r600_do_init_cp()
2193 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); in r600_do_init_cp()
2195 (unsigned int) dev_priv->gart_vm_start); in r600_do_init_cp()
2197 dev_priv->gart_buffers_offset); in r600_do_init_cp()
2199 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; in r600_do_init_cp()
2200 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle in r600_do_init_cp()
2202 dev_priv->ring.size = init->ring_size; in r600_do_init_cp()
2203 dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8); in r600_do_init_cp()
2205 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; in r600_do_init_cp()
2206 dev_priv->ring.rptr_update_l2qw = order_base_2(/* init->rptr_update */ 4096 / 8); in r600_do_init_cp()
2208 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; in r600_do_init_cp()
2209 dev_priv->ring.fetch_size_l2ow = order_base_2(/* init->fetch_size */ 32 / 16); in r600_do_init_cp()
2211 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; in r600_do_init_cp()
2213 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; in r600_do_init_cp()
2216 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
2221 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); in r600_do_init_cp()
2223 if (!dev_priv->pcigart_offset_set) { in r600_do_init_cp()
2229 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); in r600_do_init_cp()
2231 dev_priv->gart_info.bus_addr = in r600_do_init_cp()
2232 dev_priv->pcigart_offset + dev_priv->fb_location; in r600_do_init_cp()
2233 dev_priv->gart_info.mapping.offset = in r600_do_init_cp()
2234 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; in r600_do_init_cp()
2235 dev_priv->gart_info.mapping.size = in r600_do_init_cp()
2236 dev_priv->gart_info.table_size; in r600_do_init_cp()
2238 drm_legacy_ioremap_wc(&dev_priv->gart_info.mapping, dev); in r600_do_init_cp()
2239 if (!dev_priv->gart_info.mapping.handle) { in r600_do_init_cp()
2245 dev_priv->gart_info.addr = in r600_do_init_cp()
2246 dev_priv->gart_info.mapping.handle; in r600_do_init_cp()
2249 dev_priv->gart_info.addr, in r600_do_init_cp()
2250 dev_priv->pcigart_offset); in r600_do_init_cp()
2258 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_do_init_cp()
2264 if (!dev_priv->me_fw || !dev_priv->pfp_fw) { in r600_do_init_cp()
2265 int err = r600_cp_init_microcode(dev_priv); in r600_do_init_cp()
2272 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_do_init_cp()
2273 r700_cp_load_microcode(dev_priv); in r600_do_init_cp()
2275 r600_cp_load_microcode(dev_priv); in r600_do_init_cp()
2277 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); in r600_do_init_cp()
2279 dev_priv->last_buf = 0; in r600_do_init_cp()
2282 r600_test_writeback(dev_priv); in r600_do_init_cp()
2289 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_resume_cp() local
2292 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { in r600_do_resume_cp()
2294 r700_cp_load_microcode(dev_priv); in r600_do_resume_cp()
2297 r600_cp_load_microcode(dev_priv); in r600_do_resume_cp()
2299 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); in r600_do_resume_cp()
2307 int r600_do_cp_idle(drm_radeon_private_t *dev_priv) in r600_do_cp_idle() argument
2323 return r600_do_wait_for_idle(dev_priv); in r600_do_cp_idle()
2328 void r600_do_cp_start(drm_radeon_private_t *dev_priv) in r600_do_cp_start() argument
2337 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) in r600_do_cp_start()
2341 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); in r600_do_cp_start()
2352 dev_priv->cp_running = 1; in r600_do_cp_start()
2356 void r600_do_cp_reset(drm_radeon_private_t *dev_priv) in r600_do_cp_reset() argument
2363 SET_RING_HEAD(dev_priv, cur_read_ptr); in r600_do_cp_reset()
2364 dev_priv->ring.tail = cur_read_ptr; in r600_do_cp_reset()
2367 void r600_do_cp_stop(drm_radeon_private_t *dev_priv) in r600_do_cp_stop() argument
2377 dev_priv->cp_running = 0; in r600_do_cp_stop()
2383 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_indirect() local
2387 unsigned long offset = (dev_priv->gart_buffers_offset in r600_cp_dispatch_indirect()
2419 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_swap() local
2430 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) in r600_cp_dispatch_swap()
2436 src_pitch = dev_priv->back_pitch; in r600_cp_dispatch_swap()
2437 dst_pitch = dev_priv->front_pitch; in r600_cp_dispatch_swap()
2438 src = dev_priv->back_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2439 dst = dev_priv->front_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2441 src_pitch = dev_priv->front_pitch; in r600_cp_dispatch_swap()
2442 dst_pitch = dev_priv->back_pitch; in r600_cp_dispatch_swap()
2443 src = dev_priv->front_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2444 dst = dev_priv->back_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2482 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_texture() local
2489 if (!radeon_check_offset(dev_priv, tex->offset)) { in r600_cp_dispatch_texture()
2495 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { in r600_cp_dispatch_texture()
2538 src_offset = dev_priv->gart_buffers_offset + buf->offset; in r600_cp_dispatch_texture()
2570 static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) in r600_cs_id_emit() argument
2574 *id = radeon_cs_id_get(dev_priv); in r600_cs_id_emit()
2602 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_ib_free() local
2614 struct drm_radeon_private *dev_priv = dev->dev_private; in r600_cs_legacy_ioctl() local
2621 if (dev_priv == NULL) { in r600_cs_legacy_ioctl()
2625 family = dev_priv->flags & RADEON_FAMILY_MASK; in r600_cs_legacy_ioctl()
2630 mutex_lock(&dev_priv->cs_mutex); in r600_cs_legacy_ioctl()
2647 r600_cs_id_emit(dev_priv, &cs_id); in r600_cs_legacy_ioctl()
2649 mutex_unlock(&dev_priv->cs_mutex); in r600_cs_legacy_ioctl()
2655 struct drm_radeon_private *dev_priv = dev->dev_private; in r600_cs_legacy_get_tiling_conf() local
2657 *npipes = dev_priv->r600_npipes; in r600_cs_legacy_get_tiling_conf()
2658 *nbanks = dev_priv->r600_nbanks; in r600_cs_legacy_get_tiling_conf()
2659 *group_size = dev_priv->r600_group_size; in r600_cs_legacy_get_tiling_conf()