Lines Matching refs:pm
57 for (i = 0; i < rdev->pm.num_power_states; i++) { in radeon_pm_get_type_index()
58 if (rdev->pm.power_state[i].type == ps_type) { in radeon_pm_get_type_index()
65 return rdev->pm.default_power_state_index; in radeon_pm_get_type_index()
70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_pm_acpi_event_handler()
71 mutex_lock(&rdev->pm.mutex); in radeon_pm_acpi_event_handler()
73 rdev->pm.dpm.ac_power = true; in radeon_pm_acpi_event_handler()
75 rdev->pm.dpm.ac_power = false; in radeon_pm_acpi_event_handler()
78 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); in radeon_pm_acpi_event_handler()
80 mutex_unlock(&rdev->pm.mutex); in radeon_pm_acpi_event_handler()
81 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { in radeon_pm_acpi_event_handler()
82 if (rdev->pm.profile == PM_PROFILE_AUTO) { in radeon_pm_acpi_event_handler()
83 mutex_lock(&rdev->pm.mutex); in radeon_pm_acpi_event_handler()
86 mutex_unlock(&rdev->pm.mutex); in radeon_pm_acpi_event_handler()
93 switch (rdev->pm.profile) { in radeon_pm_update_profile()
95 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; in radeon_pm_update_profile()
99 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
100 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; in radeon_pm_update_profile()
102 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; in radeon_pm_update_profile()
104 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
105 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; in radeon_pm_update_profile()
107 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; in radeon_pm_update_profile()
111 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
112 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; in radeon_pm_update_profile()
114 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; in radeon_pm_update_profile()
117 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
118 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; in radeon_pm_update_profile()
120 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; in radeon_pm_update_profile()
123 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
124 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; in radeon_pm_update_profile()
126 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; in radeon_pm_update_profile()
130 if (rdev->pm.active_crtc_count == 0) { in radeon_pm_update_profile()
131 rdev->pm.requested_power_state_index = in radeon_pm_update_profile()
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; in radeon_pm_update_profile()
133 rdev->pm.requested_clock_mode_index = in radeon_pm_update_profile()
134 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; in radeon_pm_update_profile()
136 rdev->pm.requested_power_state_index = in radeon_pm_update_profile()
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; in radeon_pm_update_profile()
138 rdev->pm.requested_clock_mode_index = in radeon_pm_update_profile()
139 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; in radeon_pm_update_profile()
158 if (rdev->pm.active_crtcs) { in radeon_sync_with_vblank()
159 rdev->pm.vblank_sync = false; in radeon_sync_with_vblank()
161 rdev->irq.vblank_queue, rdev->pm.vblank_sync, in radeon_sync_with_vblank()
171 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && in radeon_set_power_state()
172 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) in radeon_set_power_state()
176 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
177 clock_info[rdev->pm.requested_clock_mode_index].sclk; in radeon_set_power_state()
178 if (sclk > rdev->pm.default_sclk) in radeon_set_power_state()
179 sclk = rdev->pm.default_sclk; in radeon_set_power_state()
185 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && in radeon_set_power_state()
187 rdev->pm.active_crtc_count && in radeon_set_power_state()
188 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || in radeon_set_power_state()
189 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) in radeon_set_power_state()
190 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
191 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; in radeon_set_power_state()
193 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
194 clock_info[rdev->pm.requested_clock_mode_index].mclk; in radeon_set_power_state()
196 if (mclk > rdev->pm.default_mclk) in radeon_set_power_state()
197 mclk = rdev->pm.default_mclk; in radeon_set_power_state()
200 if (sclk < rdev->pm.current_sclk) in radeon_set_power_state()
205 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { in radeon_set_power_state()
217 if (sclk != rdev->pm.current_sclk) { in radeon_set_power_state()
221 rdev->pm.current_sclk = sclk; in radeon_set_power_state()
226 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { in radeon_set_power_state()
230 rdev->pm.current_mclk = mclk; in radeon_set_power_state()
240 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; in radeon_set_power_state()
241 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; in radeon_set_power_state()
251 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && in radeon_pm_set_clocks()
252 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) in radeon_pm_set_clocks()
256 down_write(&rdev->pm.mclk_lock); in radeon_pm_set_clocks()
269 up_write(&rdev->pm.mclk_lock); in radeon_pm_set_clocks()
279 if (rdev->pm.active_crtcs & (1 << i)) { in radeon_pm_set_clocks()
280 rdev->pm.req_vblank |= (1 << i); in radeon_pm_set_clocks()
290 if (rdev->pm.req_vblank & (1 << i)) { in radeon_pm_set_clocks()
291 rdev->pm.req_vblank &= ~(1 << i); in radeon_pm_set_clocks()
299 if (rdev->pm.active_crtc_count) in radeon_pm_set_clocks()
302 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_pm_set_clocks()
305 up_write(&rdev->pm.mclk_lock); in radeon_pm_set_clocks()
315 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); in radeon_pm_print_states()
316 for (i = 0; i < rdev->pm.num_power_states; i++) { in radeon_pm_print_states()
317 power_state = &rdev->pm.power_state[i]; in radeon_pm_print_states()
320 if (i == rdev->pm.default_power_state_index) in radeon_pm_print_states()
349 int cp = rdev->pm.profile; in radeon_get_pm_profile()
371 mutex_lock(&rdev->pm.mutex); in radeon_set_pm_profile()
372 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { in radeon_set_pm_profile()
374 rdev->pm.profile = PM_PROFILE_DEFAULT; in radeon_set_pm_profile()
376 rdev->pm.profile = PM_PROFILE_AUTO; in radeon_set_pm_profile()
378 rdev->pm.profile = PM_PROFILE_LOW; in radeon_set_pm_profile()
380 rdev->pm.profile = PM_PROFILE_MID; in radeon_set_pm_profile()
382 rdev->pm.profile = PM_PROFILE_HIGH; in radeon_set_pm_profile()
393 mutex_unlock(&rdev->pm.mutex); in radeon_set_pm_profile()
404 int pm = rdev->pm.pm_method; in radeon_get_pm_method() local
407 (pm == PM_METHOD_DYNPM) ? "dynpm" : in radeon_get_pm_method()
408 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); in radeon_get_pm_method()
427 if (rdev->pm.pm_method == PM_METHOD_DPM) { in radeon_set_pm_method()
433 mutex_lock(&rdev->pm.mutex); in radeon_set_pm_method()
434 rdev->pm.pm_method = PM_METHOD_DYNPM; in radeon_set_pm_method()
435 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; in radeon_set_pm_method()
436 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; in radeon_set_pm_method()
437 mutex_unlock(&rdev->pm.mutex); in radeon_set_pm_method()
439 mutex_lock(&rdev->pm.mutex); in radeon_set_pm_method()
441 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; in radeon_set_pm_method()
442 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_set_pm_method()
443 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_set_pm_method()
444 mutex_unlock(&rdev->pm.mutex); in radeon_set_pm_method()
445 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); in radeon_set_pm_method()
461 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; in radeon_get_dpm_state() local
464 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : in radeon_get_dpm_state()
465 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); in radeon_get_dpm_state()
476 mutex_lock(&rdev->pm.mutex); in radeon_set_dpm_state()
478 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; in radeon_set_dpm_state()
480 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in radeon_set_dpm_state()
482 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; in radeon_set_dpm_state()
484 mutex_unlock(&rdev->pm.mutex); in radeon_set_dpm_state()
488 mutex_unlock(&rdev->pm.mutex); in radeon_set_dpm_state()
505 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; in radeon_get_dpm_forced_performance_level()
531 mutex_lock(&rdev->pm.mutex); in radeon_set_dpm_forced_performance_level()
543 if (rdev->pm.dpm.thermal_active) { in radeon_set_dpm_forced_performance_level()
552 mutex_unlock(&rdev->pm.mutex); in radeon_set_dpm_forced_performance_level()
577 if (rdev->asic->pm.get_temperature) in radeon_hwmon_show_temp()
594 temp = rdev->pm.dpm.thermal.min_temp; in radeon_hwmon_show_temp_thresh()
596 temp = rdev->pm.dpm.thermal.max_temp; in radeon_hwmon_show_temp_thresh()
619 if (rdev->pm.pm_method != PM_METHOD_DPM && in hwmon_attributes_visible()
641 switch (rdev->pm.int_thermal_type) { in radeon_hwmon_init()
650 if (rdev->asic->pm.get_temperature == NULL) in radeon_hwmon_init()
652 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, in radeon_hwmon_init()
655 if (IS_ERR(rdev->pm.int_hwmon_dev)) { in radeon_hwmon_init()
656 err = PTR_ERR(rdev->pm.int_hwmon_dev); in radeon_hwmon_init()
670 if (rdev->pm.int_hwmon_dev) in radeon_hwmon_fini()
671 hwmon_device_unregister(rdev->pm.int_hwmon_dev); in radeon_hwmon_fini()
678 pm.dpm.thermal.work); in radeon_dpm_thermal_work_handler()
682 if (!rdev->pm.dpm_enabled) in radeon_dpm_thermal_work_handler()
685 if (rdev->asic->pm.get_temperature) { in radeon_dpm_thermal_work_handler()
688 if (temp < rdev->pm.dpm.thermal.min_temp) in radeon_dpm_thermal_work_handler()
690 dpm_state = rdev->pm.dpm.user_state; in radeon_dpm_thermal_work_handler()
692 if (rdev->pm.dpm.thermal.high_to_low) in radeon_dpm_thermal_work_handler()
694 dpm_state = rdev->pm.dpm.user_state; in radeon_dpm_thermal_work_handler()
696 mutex_lock(&rdev->pm.mutex); in radeon_dpm_thermal_work_handler()
698 rdev->pm.dpm.thermal_active = true; in radeon_dpm_thermal_work_handler()
700 rdev->pm.dpm.thermal_active = false; in radeon_dpm_thermal_work_handler()
701 rdev->pm.dpm.state = dpm_state; in radeon_dpm_thermal_work_handler()
702 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_thermal_work_handler()
709 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? in radeon_dpm_single_display()
740 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in radeon_dpm_pick_power_state()
741 ps = &rdev->pm.dpm.ps[i]; in radeon_dpm_pick_power_state()
774 if (rdev->pm.dpm.uvd_ps) in radeon_dpm_pick_power_state()
775 return rdev->pm.dpm.uvd_ps; in radeon_dpm_pick_power_state()
795 return rdev->pm.dpm.boot_ps; in radeon_dpm_pick_power_state()
824 if (rdev->pm.dpm.uvd_ps) { in radeon_dpm_pick_power_state()
825 return rdev->pm.dpm.uvd_ps; in radeon_dpm_pick_power_state()
857 if (!rdev->pm.dpm_enabled) in radeon_dpm_change_power_state_locked()
860 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { in radeon_dpm_change_power_state_locked()
862 if ((!rdev->pm.dpm.thermal_active) && in radeon_dpm_change_power_state_locked()
863 (!rdev->pm.dpm.uvd_active)) in radeon_dpm_change_power_state_locked()
864 rdev->pm.dpm.state = rdev->pm.dpm.user_state; in radeon_dpm_change_power_state_locked()
866 dpm_state = rdev->pm.dpm.state; in radeon_dpm_change_power_state_locked()
870 rdev->pm.dpm.requested_ps = ps; in radeon_dpm_change_power_state_locked()
875 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { in radeon_dpm_change_power_state_locked()
877 if (ps->vce_active != rdev->pm.dpm.vce_active) in radeon_dpm_change_power_state_locked()
880 if (rdev->pm.dpm.single_display != single_display) in radeon_dpm_change_power_state_locked()
886 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { in radeon_dpm_change_power_state_locked()
891 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; in radeon_dpm_change_power_state_locked()
892 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; in radeon_dpm_change_power_state_locked()
900 if (rdev->pm.dpm.new_active_crtcs == in radeon_dpm_change_power_state_locked()
901 rdev->pm.dpm.current_active_crtcs) { in radeon_dpm_change_power_state_locked()
904 if ((rdev->pm.dpm.current_active_crtc_count > 1) && in radeon_dpm_change_power_state_locked()
905 (rdev->pm.dpm.new_active_crtc_count > 1)) { in radeon_dpm_change_power_state_locked()
910 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; in radeon_dpm_change_power_state_locked()
911 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; in radeon_dpm_change_power_state_locked()
921 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); in radeon_dpm_change_power_state_locked()
923 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); in radeon_dpm_change_power_state_locked()
927 down_write(&rdev->pm.mclk_lock); in radeon_dpm_change_power_state_locked()
931 ps->vce_active = rdev->pm.dpm.vce_active; in radeon_dpm_change_power_state_locked()
953 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; in radeon_dpm_change_power_state_locked()
957 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; in radeon_dpm_change_power_state_locked()
958 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; in radeon_dpm_change_power_state_locked()
959 rdev->pm.dpm.single_display = single_display; in radeon_dpm_change_power_state_locked()
962 if (rdev->pm.dpm.thermal_active) { in radeon_dpm_change_power_state_locked()
963 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; in radeon_dpm_change_power_state_locked()
967 rdev->pm.dpm.forced_level = level; in radeon_dpm_change_power_state_locked()
970 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); in radeon_dpm_change_power_state_locked()
976 up_write(&rdev->pm.mclk_lock); in radeon_dpm_change_power_state_locked()
985 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
988 enable |= rdev->pm.dpm.sd > 0; in radeon_dpm_enable_uvd()
989 enable |= rdev->pm.dpm.hd > 0; in radeon_dpm_enable_uvd()
992 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
995 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
996 rdev->pm.dpm.uvd_active = true; in radeon_dpm_enable_uvd()
999 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) in radeon_dpm_enable_uvd()
1001 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) in radeon_dpm_enable_uvd()
1003 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) in radeon_dpm_enable_uvd()
1005 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) in radeon_dpm_enable_uvd()
1010 rdev->pm.dpm.state = dpm_state; in radeon_dpm_enable_uvd()
1011 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1013 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1014 rdev->pm.dpm.uvd_active = false; in radeon_dpm_enable_uvd()
1015 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1025 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_vce()
1026 rdev->pm.dpm.vce_active = true; in radeon_dpm_enable_vce()
1028 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; in radeon_dpm_enable_vce()
1029 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_vce()
1031 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_vce()
1032 rdev->pm.dpm.vce_active = false; in radeon_dpm_enable_vce()
1033 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_vce()
1041 mutex_lock(&rdev->pm.mutex); in radeon_pm_suspend_old()
1042 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { in radeon_pm_suspend_old()
1043 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) in radeon_pm_suspend_old()
1044 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; in radeon_pm_suspend_old()
1046 mutex_unlock(&rdev->pm.mutex); in radeon_pm_suspend_old()
1048 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); in radeon_pm_suspend_old()
1053 mutex_lock(&rdev->pm.mutex); in radeon_pm_suspend_dpm()
1057 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; in radeon_pm_suspend_dpm()
1058 rdev->pm.dpm_enabled = false; in radeon_pm_suspend_dpm()
1059 mutex_unlock(&rdev->pm.mutex); in radeon_pm_suspend_dpm()
1064 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_suspend()
1076 if (rdev->pm.default_vddc) in radeon_pm_resume_old()
1077 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_resume_old()
1079 if (rdev->pm.default_vddci) in radeon_pm_resume_old()
1080 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, in radeon_pm_resume_old()
1082 if (rdev->pm.default_sclk) in radeon_pm_resume_old()
1083 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); in radeon_pm_resume_old()
1084 if (rdev->pm.default_mclk) in radeon_pm_resume_old()
1085 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); in radeon_pm_resume_old()
1088 mutex_lock(&rdev->pm.mutex); in radeon_pm_resume_old()
1089 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; in radeon_pm_resume_old()
1090 rdev->pm.current_clock_mode_index = 0; in radeon_pm_resume_old()
1091 rdev->pm.current_sclk = rdev->pm.default_sclk; in radeon_pm_resume_old()
1092 rdev->pm.current_mclk = rdev->pm.default_mclk; in radeon_pm_resume_old()
1093 if (rdev->pm.power_state) { in radeon_pm_resume_old()
1094 …rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].vol… in radeon_pm_resume_old()
1095 …rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].vo… in radeon_pm_resume_old()
1097 if (rdev->pm.pm_method == PM_METHOD_DYNPM in radeon_pm_resume_old()
1098 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { in radeon_pm_resume_old()
1099 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; in radeon_pm_resume_old()
1100 schedule_delayed_work(&rdev->pm.dynpm_idle_work, in radeon_pm_resume_old()
1103 mutex_unlock(&rdev->pm.mutex); in radeon_pm_resume_old()
1112 mutex_lock(&rdev->pm.mutex); in radeon_pm_resume_dpm()
1113 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; in radeon_pm_resume_dpm()
1116 mutex_unlock(&rdev->pm.mutex); in radeon_pm_resume_dpm()
1119 rdev->pm.dpm_enabled = true; in radeon_pm_resume_dpm()
1127 if (rdev->pm.default_vddc) in radeon_pm_resume_dpm()
1128 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_resume_dpm()
1130 if (rdev->pm.default_vddci) in radeon_pm_resume_dpm()
1131 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, in radeon_pm_resume_dpm()
1133 if (rdev->pm.default_sclk) in radeon_pm_resume_dpm()
1134 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); in radeon_pm_resume_dpm()
1135 if (rdev->pm.default_mclk) in radeon_pm_resume_dpm()
1136 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); in radeon_pm_resume_dpm()
1142 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_resume()
1152 rdev->pm.profile = PM_PROFILE_DEFAULT; in radeon_pm_init_old()
1153 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; in radeon_pm_init_old()
1154 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_pm_init_old()
1155 rdev->pm.dynpm_can_upclock = true; in radeon_pm_init_old()
1156 rdev->pm.dynpm_can_downclock = true; in radeon_pm_init_old()
1157 rdev->pm.default_sclk = rdev->clock.default_sclk; in radeon_pm_init_old()
1158 rdev->pm.default_mclk = rdev->clock.default_mclk; in radeon_pm_init_old()
1159 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_old()
1160 rdev->pm.current_mclk = rdev->clock.default_mclk; in radeon_pm_init_old()
1161 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; in radeon_pm_init_old()
1174 if (rdev->pm.default_vddc) in radeon_pm_init_old()
1175 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_init_old()
1177 if (rdev->pm.default_vddci) in radeon_pm_init_old()
1178 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, in radeon_pm_init_old()
1180 if (rdev->pm.default_sclk) in radeon_pm_init_old()
1181 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); in radeon_pm_init_old()
1182 if (rdev->pm.default_mclk) in radeon_pm_init_old()
1183 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); in radeon_pm_init_old()
1192 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); in radeon_pm_init_old()
1194 if (rdev->pm.num_power_states > 1) { in radeon_pm_init_old()
1209 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in radeon_dpm_print_power_states()
1211 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); in radeon_dpm_print_power_states()
1220 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in radeon_pm_init_dpm()
1221 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in radeon_pm_init_dpm()
1222 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; in radeon_pm_init_dpm()
1223 rdev->pm.default_sclk = rdev->clock.default_sclk; in radeon_pm_init_dpm()
1224 rdev->pm.default_mclk = rdev->clock.default_mclk; in radeon_pm_init_dpm()
1225 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_dpm()
1226 rdev->pm.current_mclk = rdev->clock.default_mclk; in radeon_pm_init_dpm()
1227 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; in radeon_pm_init_dpm()
1239 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); in radeon_pm_init_dpm()
1240 mutex_lock(&rdev->pm.mutex); in radeon_pm_init_dpm()
1242 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; in radeon_pm_init_dpm()
1247 mutex_unlock(&rdev->pm.mutex); in radeon_pm_init_dpm()
1250 rdev->pm.dpm_enabled = true; in radeon_pm_init_dpm()
1261 rdev->pm.dpm_enabled = false; in radeon_pm_init_dpm()
1265 if (rdev->pm.default_vddc) in radeon_pm_init_dpm()
1266 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_init_dpm()
1268 if (rdev->pm.default_vddci) in radeon_pm_init_dpm()
1269 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, in radeon_pm_init_dpm()
1271 if (rdev->pm.default_sclk) in radeon_pm_init_dpm()
1272 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); in radeon_pm_init_dpm()
1273 if (rdev->pm.default_mclk) in radeon_pm_init_dpm()
1274 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); in radeon_pm_init_dpm()
1325 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1329 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1331 rdev->pm.pm_method = PM_METHOD_DPM; in radeon_pm_init()
1333 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1363 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1367 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1369 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1371 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1373 rdev->pm.pm_method = PM_METHOD_DPM; in radeon_pm_init()
1377 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1381 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_init()
1391 if (rdev->pm.pm_method == PM_METHOD_DPM) { in radeon_pm_late_init()
1392 if (rdev->pm.dpm_enabled) { in radeon_pm_late_init()
1393 if (!rdev->pm.sysfs_initialized) { in radeon_pm_late_init()
1408 rdev->pm.sysfs_initialized = true; in radeon_pm_late_init()
1411 mutex_lock(&rdev->pm.mutex); in radeon_pm_late_init()
1413 mutex_unlock(&rdev->pm.mutex); in radeon_pm_late_init()
1415 rdev->pm.dpm_enabled = false; in radeon_pm_late_init()
1425 if ((rdev->pm.num_power_states > 1) && in radeon_pm_late_init()
1426 (!rdev->pm.sysfs_initialized)) { in radeon_pm_late_init()
1435 rdev->pm.sysfs_initialized = true; in radeon_pm_late_init()
1443 if (rdev->pm.num_power_states > 1) { in radeon_pm_fini_old()
1444 mutex_lock(&rdev->pm.mutex); in radeon_pm_fini_old()
1445 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { in radeon_pm_fini_old()
1446 rdev->pm.profile = PM_PROFILE_DEFAULT; in radeon_pm_fini_old()
1449 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { in radeon_pm_fini_old()
1451 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; in radeon_pm_fini_old()
1452 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; in radeon_pm_fini_old()
1455 mutex_unlock(&rdev->pm.mutex); in radeon_pm_fini_old()
1457 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); in radeon_pm_fini_old()
1464 kfree(rdev->pm.power_state); in radeon_pm_fini_old()
1469 if (rdev->pm.num_power_states > 1) { in radeon_pm_fini_dpm()
1470 mutex_lock(&rdev->pm.mutex); in radeon_pm_fini_dpm()
1472 mutex_unlock(&rdev->pm.mutex); in radeon_pm_fini_dpm()
1483 kfree(rdev->pm.power_state); in radeon_pm_fini_dpm()
1488 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_fini()
1500 if (rdev->pm.num_power_states < 2) in radeon_pm_compute_clocks_old()
1503 mutex_lock(&rdev->pm.mutex); in radeon_pm_compute_clocks_old()
1505 rdev->pm.active_crtcs = 0; in radeon_pm_compute_clocks_old()
1506 rdev->pm.active_crtc_count = 0; in radeon_pm_compute_clocks_old()
1512 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_old()
1513 rdev->pm.active_crtc_count++; in radeon_pm_compute_clocks_old()
1518 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { in radeon_pm_compute_clocks_old()
1521 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { in radeon_pm_compute_clocks_old()
1522 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { in radeon_pm_compute_clocks_old()
1523 if (rdev->pm.active_crtc_count > 1) { in radeon_pm_compute_clocks_old()
1524 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { in radeon_pm_compute_clocks_old()
1525 cancel_delayed_work(&rdev->pm.dynpm_idle_work); in radeon_pm_compute_clocks_old()
1527 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; in radeon_pm_compute_clocks_old()
1528 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; in radeon_pm_compute_clocks_old()
1534 } else if (rdev->pm.active_crtc_count == 1) { in radeon_pm_compute_clocks_old()
1537 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { in radeon_pm_compute_clocks_old()
1538 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; in radeon_pm_compute_clocks_old()
1539 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; in radeon_pm_compute_clocks_old()
1543 schedule_delayed_work(&rdev->pm.dynpm_idle_work, in radeon_pm_compute_clocks_old()
1545 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { in radeon_pm_compute_clocks_old()
1546 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; in radeon_pm_compute_clocks_old()
1547 schedule_delayed_work(&rdev->pm.dynpm_idle_work, in radeon_pm_compute_clocks_old()
1552 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { in radeon_pm_compute_clocks_old()
1553 cancel_delayed_work(&rdev->pm.dynpm_idle_work); in radeon_pm_compute_clocks_old()
1555 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; in radeon_pm_compute_clocks_old()
1556 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; in radeon_pm_compute_clocks_old()
1564 mutex_unlock(&rdev->pm.mutex); in radeon_pm_compute_clocks_old()
1573 if (!rdev->pm.dpm_enabled) in radeon_pm_compute_clocks_dpm()
1576 mutex_lock(&rdev->pm.mutex); in radeon_pm_compute_clocks_dpm()
1579 rdev->pm.dpm.new_active_crtcs = 0; in radeon_pm_compute_clocks_dpm()
1580 rdev->pm.dpm.new_active_crtc_count = 0; in radeon_pm_compute_clocks_dpm()
1586 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_dpm()
1587 rdev->pm.dpm.new_active_crtc_count++; in radeon_pm_compute_clocks_dpm()
1594 rdev->pm.dpm.ac_power = true; in radeon_pm_compute_clocks_dpm()
1596 rdev->pm.dpm.ac_power = false; in radeon_pm_compute_clocks_dpm()
1600 mutex_unlock(&rdev->pm.mutex); in radeon_pm_compute_clocks_dpm()
1606 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_compute_clocks()
1621 if (rdev->pm.active_crtcs & (1 << crtc)) { in radeon_pm_in_vbl()
1648 pm.dynpm_idle_work.work); in radeon_dynpm_idle_work_handler()
1651 mutex_lock(&rdev->pm.mutex); in radeon_dynpm_idle_work_handler()
1652 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { in radeon_dynpm_idle_work_handler()
1667 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { in radeon_dynpm_idle_work_handler()
1668 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_dynpm_idle_work_handler()
1669 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && in radeon_dynpm_idle_work_handler()
1670 rdev->pm.dynpm_can_upclock) { in radeon_dynpm_idle_work_handler()
1671 rdev->pm.dynpm_planned_action = in radeon_dynpm_idle_work_handler()
1673 rdev->pm.dynpm_action_timeout = jiffies + in radeon_dynpm_idle_work_handler()
1677 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { in radeon_dynpm_idle_work_handler()
1678 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_dynpm_idle_work_handler()
1679 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && in radeon_dynpm_idle_work_handler()
1680 rdev->pm.dynpm_can_downclock) { in radeon_dynpm_idle_work_handler()
1681 rdev->pm.dynpm_planned_action = in radeon_dynpm_idle_work_handler()
1683 rdev->pm.dynpm_action_timeout = jiffies + in radeon_dynpm_idle_work_handler()
1691 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && in radeon_dynpm_idle_work_handler()
1692 jiffies > rdev->pm.dynpm_action_timeout) { in radeon_dynpm_idle_work_handler()
1697 schedule_delayed_work(&rdev->pm.dynpm_idle_work, in radeon_dynpm_idle_work_handler()
1700 mutex_unlock(&rdev->pm.mutex); in radeon_dynpm_idle_work_handler()
1719 } else if (rdev->pm.dpm_enabled) { in radeon_debugfs_pm_info()
1720 mutex_lock(&rdev->pm.mutex); in radeon_debugfs_pm_info()
1725 mutex_unlock(&rdev->pm.mutex); in radeon_debugfs_pm_info()
1727 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); in radeon_debugfs_pm_info()
1730 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); in radeon_debugfs_pm_info()
1733 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); in radeon_debugfs_pm_info()
1734 if (rdev->asic->pm.get_memory_clock) in radeon_debugfs_pm_info()
1736 if (rdev->pm.current_vddc) in radeon_debugfs_pm_info()
1737 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); in radeon_debugfs_pm_info()
1738 if (rdev->asic->pm.get_pcie_lanes) in radeon_debugfs_pm_info()