43 			   struct radeon_ring *ring)  in vce_v1_0_get_rptr()  argument
45 	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)  in vce_v1_0_get_rptr()
60 			   struct radeon_ring *ring)  in vce_v1_0_get_wptr()  argument
62 	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)  in vce_v1_0_get_wptr()
77 		       struct radeon_ring *ring)  in vce_v1_0_set_wptr()  argument
79 	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)  in vce_v1_0_set_wptr()
80 		WREG32(VCE_RB_WPTR, ring->wptr);  in vce_v1_0_set_wptr()
82 		WREG32(VCE_RB_WPTR2, ring->wptr);  in vce_v1_0_set_wptr()
94 	struct radeon_ring *ring;  in vce_v1_0_start()  local
100 	ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];  in vce_v1_0_start()
101 	WREG32(VCE_RB_RPTR, ring->wptr);  in vce_v1_0_start()
102 	WREG32(VCE_RB_WPTR, ring->wptr);  in vce_v1_0_start()
103 	WREG32(VCE_RB_BASE_LO, ring->gpu_addr);  in vce_v1_0_start()
104 	WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v1_0_start()
105 	WREG32(VCE_RB_SIZE, ring->ring_size / 4);  in vce_v1_0_start()
107 	ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];  in vce_v1_0_start()
108 	WREG32(VCE_RB_RPTR2, ring->wptr);  in vce_v1_0_start()
109 	WREG32(VCE_RB_WPTR2, ring->wptr);  in vce_v1_0_start()
110 	WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v1_0_start()
111 	WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v1_0_start()
112 	WREG32(VCE_RB_SIZE2, ring->ring_size / 4);  in vce_v1_0_start()
161 	struct radeon_ring *ring;  in vce_v1_0_init()  local
168 	ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];  in vce_v1_0_init()
169 	ring->ready = true;  in vce_v1_0_init()
170 	r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring);  in vce_v1_0_init()
172 		ring->ready = false;  in vce_v1_0_init()
176 	ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];  in vce_v1_0_init()
177 	ring->ready = true;  in vce_v1_0_init()
178 	r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring);  in vce_v1_0_init()
180 		ring->ready = false;  in vce_v1_0_init()