Lines Matching refs:dc
141 static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, in tegra_dc_setup_window() argument
159 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_setup_window()
161 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
162 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
165 tegra_dc_writel(dc, value, DC_WIN_POSITION); in tegra_dc_setup_window()
168 tegra_dc_writel(dc, value, DC_WIN_SIZE); in tegra_dc_setup_window()
176 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); in tegra_dc_setup_window()
189 tegra_dc_writel(dc, value, DC_WIN_DDA_INC); in tegra_dc_setup_window()
194 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); in tegra_dc_setup_window()
195 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); in tegra_dc_setup_window()
197 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); in tegra_dc_setup_window()
198 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); in tegra_dc_setup_window()
200 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
203 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
204 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
206 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
208 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
214 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); in tegra_dc_setup_window()
215 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); in tegra_dc_setup_window()
217 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
235 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); in tegra_dc_setup_window()
253 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); in tegra_dc_setup_window()
260 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); in tegra_dc_setup_window()
261 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); in tegra_dc_setup_window()
262 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); in tegra_dc_setup_window()
263 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); in tegra_dc_setup_window()
264 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); in tegra_dc_setup_window()
265 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); in tegra_dc_setup_window()
266 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); in tegra_dc_setup_window()
267 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); in tegra_dc_setup_window()
277 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_dc_setup_window()
283 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); in tegra_dc_setup_window()
284 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); in tegra_dc_setup_window()
288 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
289 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
290 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
294 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
295 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
296 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
300 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
301 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
302 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
306 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL); in tegra_dc_setup_window()
307 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL); in tegra_dc_setup_window()
319 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_plane_update() local
359 return tegra_dc_setup_window(dc, p->index, &window); in tegra_plane_update()
364 struct tegra_dc *dc = to_tegra_dc(plane->crtc); in tegra_plane_disable() local
372 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_plane_disable()
374 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); in tegra_plane_disable()
376 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_plane_disable()
378 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL); in tegra_plane_disable()
379 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL); in tegra_plane_disable()
409 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) in tegra_dc_add_planes() argument
423 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe, in tegra_dc_add_planes()
435 static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, in tegra_dc_set_base() argument
449 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_set_base()
454 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); in tegra_dc_set_base()
455 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); in tegra_dc_set_base()
458 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); in tegra_dc_set_base()
459 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP); in tegra_dc_set_base()
461 if (dc->soc->supports_block_linear) { in tegra_dc_set_base()
479 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); in tegra_dc_set_base()
497 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); in tegra_dc_set_base()
502 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); in tegra_dc_set_base()
504 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_dc_set_base()
508 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); in tegra_dc_set_base()
510 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_dc_set_base()
513 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); in tegra_dc_set_base()
514 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); in tegra_dc_set_base()
517 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_dc_set_base()
520 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_dc_set_base()
525 void tegra_dc_enable_vblank(struct tegra_dc *dc) in tegra_dc_enable_vblank() argument
529 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_enable_vblank()
531 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
533 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
535 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_enable_vblank()
538 void tegra_dc_disable_vblank(struct tegra_dc *dc) in tegra_dc_disable_vblank() argument
542 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_disable_vblank()
544 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
546 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
548 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_disable_vblank()
556 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_cursor_set2() local
560 if (!dc->soc->supports_cursor) in tegra_dc_cursor_set2()
600 tegra_dc_writel(dc, value | addr, DC_DISP_CURSOR_START_ADDR); in tegra_dc_cursor_set2()
603 tegra_dc_writel(dc, high, DC_DISP_CURSOR_START_ADDR_HI); in tegra_dc_cursor_set2()
606 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_dc_cursor_set2()
608 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dc_cursor_set2()
610 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_dc_cursor_set2()
617 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_dc_cursor_set2()
619 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_dc_cursor_set2()
621 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dc_cursor_set2()
624 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_cursor_set2()
625 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_cursor_set2()
627 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_cursor_set2()
628 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_cursor_set2()
635 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_cursor_move() local
638 if (!dc->soc->supports_cursor) in tegra_dc_cursor_move()
642 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_dc_cursor_move()
644 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_cursor_move()
645 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_cursor_move()
648 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_cursor_move()
649 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_cursor_move()
654 static void tegra_dc_finish_page_flip(struct tegra_dc *dc) in tegra_dc_finish_page_flip() argument
656 struct drm_device *drm = dc->base.dev; in tegra_dc_finish_page_flip()
657 struct drm_crtc *crtc = &dc->base; in tegra_dc_finish_page_flip()
661 if (!dc->event) in tegra_dc_finish_page_flip()
667 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
668 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); in tegra_dc_finish_page_flip()
669 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
673 drm_send_vblank_event(drm, dc->pipe, dc->event); in tegra_dc_finish_page_flip()
674 drm_vblank_put(drm, dc->pipe); in tegra_dc_finish_page_flip()
675 dc->event = NULL; in tegra_dc_finish_page_flip()
682 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_cancel_page_flip() local
688 if (dc->event && dc->event->base.file_priv == file) { in tegra_dc_cancel_page_flip()
689 dc->event->base.destroy(&dc->event->base); in tegra_dc_cancel_page_flip()
690 drm_vblank_put(drm, dc->pipe); in tegra_dc_cancel_page_flip()
691 dc->event = NULL; in tegra_dc_cancel_page_flip()
700 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_page_flip() local
703 if (dc->event) in tegra_dc_page_flip()
707 event->pipe = dc->pipe; in tegra_dc_page_flip()
708 dc->event = event; in tegra_dc_page_flip()
709 drm_vblank_get(drm, dc->pipe); in tegra_dc_page_flip()
712 tegra_dc_set_base(dc, 0, 0, fb); in tegra_dc_page_flip()
764 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
771 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
774 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
778 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
782 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
786 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
789 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
798 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_setup_clk() local
818 err = tegra_output_setup_clock(output, dc->clk, pclk, &div); in tegra_crtc_setup_clk()
820 dev_err(dc->dev, "failed to setup clock: %ld\n", err); in tegra_crtc_setup_clk()
824 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); in tegra_crtc_setup_clk()
827 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_crtc_setup_clk()
838 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_mode_set() local
845 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err); in tegra_crtc_mode_set()
850 tegra_dc_set_timings(dc, mode); in tegra_crtc_mode_set()
853 if (dc->soc->supports_interlacing) { in tegra_crtc_mode_set()
854 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_mode_set()
856 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_mode_set()
875 err = tegra_dc_setup_window(dc, 0, &window); in tegra_crtc_mode_set()
877 dev_err(dc->dev, "failed to enable root plane\n"); in tegra_crtc_mode_set()
885 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_mode_set_base() local
887 return tegra_dc_set_base(dc, x, y, crtc->primary->fb); in tegra_crtc_mode_set_base()
892 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_prepare() local
899 reset_control_deassert(dc->rst); in tegra_crtc_prepare()
902 if (dc->pipe) in tegra_crtc_prepare()
908 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_prepare()
909 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_prepare()
912 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_prepare()
916 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_prepare()
921 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_prepare()
925 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_prepare()
928 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_prepare()
931 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_prepare()
936 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_commit() local
940 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_commit()
943 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_commit()
964 struct tegra_dc *dc = data; in tegra_dc_irq() local
967 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
968 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
980 drm_handle_vblank(dc->base.dev, dc->pipe); in tegra_dc_irq()
981 tegra_dc_finish_page_flip(dc); in tegra_dc_irq()
996 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1000 tegra_dc_readl(dc, name)) in tegra_dc_show_regs()
1224 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) in tegra_dc_debugfs_init() argument
1230 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); in tegra_dc_debugfs_init()
1231 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); in tegra_dc_debugfs_init()
1234 if (!dc->debugfs) in tegra_dc_debugfs_init()
1237 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_debugfs_init()
1239 if (!dc->debugfs_files) { in tegra_dc_debugfs_init()
1245 dc->debugfs_files[i].data = dc; in tegra_dc_debugfs_init()
1247 err = drm_debugfs_create_files(dc->debugfs_files, in tegra_dc_debugfs_init()
1249 dc->debugfs, minor); in tegra_dc_debugfs_init()
1253 dc->minor = minor; in tegra_dc_debugfs_init()
1258 kfree(dc->debugfs_files); in tegra_dc_debugfs_init()
1259 dc->debugfs_files = NULL; in tegra_dc_debugfs_init()
1261 debugfs_remove(dc->debugfs); in tegra_dc_debugfs_init()
1262 dc->debugfs = NULL; in tegra_dc_debugfs_init()
1267 static int tegra_dc_debugfs_exit(struct tegra_dc *dc) in tegra_dc_debugfs_exit() argument
1269 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), in tegra_dc_debugfs_exit()
1270 dc->minor); in tegra_dc_debugfs_exit()
1271 dc->minor = NULL; in tegra_dc_debugfs_exit()
1273 kfree(dc->debugfs_files); in tegra_dc_debugfs_exit()
1274 dc->debugfs_files = NULL; in tegra_dc_debugfs_exit()
1276 debugfs_remove(dc->debugfs); in tegra_dc_debugfs_exit()
1277 dc->debugfs = NULL; in tegra_dc_debugfs_exit()
1285 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
1289 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs); in tegra_dc_init()
1290 drm_mode_crtc_set_gamma_size(&dc->base, 256); in tegra_dc_init()
1291 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
1297 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
1298 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
1300 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
1302 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
1306 err = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
1311 err = tegra_dc_debugfs_init(dc, drm->primary); in tegra_dc_init()
1313 dev_err(dc->dev, "debugfs setup failed: %d\n", err); in tegra_dc_init()
1316 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
1317 dev_name(dc->dev), dc); in tegra_dc_init()
1319 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
1329 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
1332 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
1335 err = tegra_dc_debugfs_exit(dc); in tegra_dc_exit()
1337 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); in tegra_dc_exit()
1340 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
1342 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
1398 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
1404 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
1406 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
1421 if (np == dc->dev->of_node) in tegra_dc_parse_dt()
1428 dc->pipe = value; in tegra_dc_parse_dt()
1437 struct tegra_dc *dc; in tegra_dc_probe() local
1440 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
1441 if (!dc) in tegra_dc_probe()
1448 spin_lock_init(&dc->lock); in tegra_dc_probe()
1449 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
1450 dc->dev = &pdev->dev; in tegra_dc_probe()
1451 dc->soc = id->data; in tegra_dc_probe()
1453 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
1457 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
1458 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
1460 return PTR_ERR(dc->clk); in tegra_dc_probe()
1463 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
1464 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
1466 return PTR_ERR(dc->rst); in tegra_dc_probe()
1469 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
1474 dc->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_dc_probe()
1475 if (IS_ERR(dc->regs)) in tegra_dc_probe()
1476 return PTR_ERR(dc->regs); in tegra_dc_probe()
1478 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
1479 if (dc->irq < 0) { in tegra_dc_probe()
1484 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
1485 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
1486 dc->client.dev = &pdev->dev; in tegra_dc_probe()
1488 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
1494 err = host1x_client_register(&dc->client); in tegra_dc_probe()
1501 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
1508 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
1511 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
1518 err = tegra_dc_rgb_remove(dc); in tegra_dc_remove()
1524 reset_control_assert(dc->rst); in tegra_dc_remove()
1525 clk_disable_unprepare(dc->clk); in tegra_dc_remove()