Lines Matching refs:dsi
75 static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi, in tegra_dsi_readl() argument
78 return readl(dsi->regs + (reg << 2)); in tegra_dsi_readl()
81 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value, in tegra_dsi_writel() argument
84 writel(value, dsi->regs + (reg << 2)); in tegra_dsi_writel()
90 struct tegra_dsi *dsi = node->info_ent->data; in tegra_dsi_show_regs() local
94 tegra_dsi_readl(dsi, name)) in tegra_dsi_show_regs()
187 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi, in tegra_dsi_debugfs_init() argument
190 const char *name = dev_name(dsi->dev); in tegra_dsi_debugfs_init()
194 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root); in tegra_dsi_debugfs_init()
195 if (!dsi->debugfs) in tegra_dsi_debugfs_init()
198 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dsi_debugfs_init()
200 if (!dsi->debugfs_files) { in tegra_dsi_debugfs_init()
206 dsi->debugfs_files[i].data = dsi; in tegra_dsi_debugfs_init()
208 err = drm_debugfs_create_files(dsi->debugfs_files, in tegra_dsi_debugfs_init()
210 dsi->debugfs, minor); in tegra_dsi_debugfs_init()
214 dsi->minor = minor; in tegra_dsi_debugfs_init()
219 kfree(dsi->debugfs_files); in tegra_dsi_debugfs_init()
220 dsi->debugfs_files = NULL; in tegra_dsi_debugfs_init()
222 debugfs_remove(dsi->debugfs); in tegra_dsi_debugfs_init()
223 dsi->debugfs = NULL; in tegra_dsi_debugfs_init()
228 static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi) in tegra_dsi_debugfs_exit() argument
230 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files), in tegra_dsi_debugfs_exit()
231 dsi->minor); in tegra_dsi_debugfs_exit()
232 dsi->minor = NULL; in tegra_dsi_debugfs_exit()
234 kfree(dsi->debugfs_files); in tegra_dsi_debugfs_exit()
235 dsi->debugfs_files = NULL; in tegra_dsi_debugfs_exit()
237 debugfs_remove(dsi->debugfs); in tegra_dsi_debugfs_exit()
238 dsi->debugfs = NULL; in tegra_dsi_debugfs_exit()
321 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi) in tegra_dsi_set_phy_timing() argument
328 rate = clk_get_rate(dsi->clk); in tegra_dsi_set_phy_timing()
340 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); in tegra_dsi_set_phy_timing()
354 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); in tegra_dsi_set_phy_timing()
360 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); in tegra_dsi_set_phy_timing()
365 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); in tegra_dsi_set_phy_timing()
370 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); in tegra_dsi_set_phy_timing()
434 struct tegra_dsi *dsi = to_dsi(output); in tegra_output_dsi_enable() local
440 if (dsi->enabled) in tegra_output_dsi_enable()
443 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { in tegra_output_dsi_enable()
451 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); in tegra_output_dsi_enable()
455 err = tegra_dsi_get_format(dsi->format, &format); in tegra_output_dsi_enable()
459 err = clk_enable(dsi->clk); in tegra_output_dsi_enable()
463 reset_control_deassert(dsi->rst); in tegra_output_dsi_enable()
466 DSI_CONTROL_LANES(dsi->lanes - 1) | in tegra_output_dsi_enable()
468 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_output_dsi_enable()
470 tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD); in tegra_output_dsi_enable()
474 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_output_dsi_enable()
476 value = tegra_dsi_readl(dsi, DSI_CONTROL); in tegra_output_dsi_enable()
477 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) in tegra_output_dsi_enable()
483 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_output_dsi_enable()
485 err = tegra_dsi_set_phy_timing(dsi); in tegra_output_dsi_enable()
490 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); in tegra_output_dsi_enable()
507 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); in tegra_output_dsi_enable()
508 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); in tegra_output_dsi_enable()
509 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); in tegra_output_dsi_enable()
510 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); in tegra_output_dsi_enable()
513 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); in tegra_output_dsi_enable()
534 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_output_dsi_enable()
536 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_output_dsi_enable()
538 dsi->enabled = true; in tegra_output_dsi_enable()
546 struct tegra_dsi *dsi = to_dsi(output); in tegra_output_dsi_disable() local
549 if (!dsi->enabled) in tegra_output_dsi_disable()
553 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_output_dsi_disable()
555 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_output_dsi_disable()
579 clk_disable(dsi->clk); in tegra_output_dsi_disable()
581 dsi->enabled = false; in tegra_output_dsi_disable()
593 struct tegra_dsi *dsi = to_dsi(output); in tegra_output_dsi_setup_clock() local
597 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); in tegra_output_dsi_setup_clock()
601 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, dsi->lanes); in tegra_output_dsi_setup_clock()
606 bclk = (pclk * mul) / (div * dsi->lanes); in tegra_output_dsi_setup_clock()
620 err = clk_set_parent(clk, dsi->clk_parent); in tegra_output_dsi_setup_clock()
622 dev_err(dsi->dev, "failed to set parent clock: %d\n", err); in tegra_output_dsi_setup_clock()
626 err = clk_set_rate(dsi->clk_parent, plld); in tegra_output_dsi_setup_clock()
628 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n", in tegra_output_dsi_setup_clock()
643 *divp = ((8 * mul) / (div * dsi->lanes)) - 2; in tegra_output_dsi_setup_clock()
653 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); in tegra_output_dsi_setup_clock()
658 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); in tegra_output_dsi_setup_clock()
661 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); in tegra_output_dsi_setup_clock()
686 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) in tegra_dsi_pad_enable() argument
691 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); in tegra_dsi_pad_enable()
696 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) in tegra_dsi_pad_calibrate() argument
700 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); in tegra_dsi_pad_calibrate()
701 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); in tegra_dsi_pad_calibrate()
702 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); in tegra_dsi_pad_calibrate()
703 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); in tegra_dsi_pad_calibrate()
704 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); in tegra_dsi_pad_calibrate()
707 tegra_dsi_pad_enable(dsi); in tegra_dsi_pad_calibrate()
712 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); in tegra_dsi_pad_calibrate()
714 return tegra_mipi_calibrate(dsi->mipi); in tegra_dsi_pad_calibrate()
720 struct tegra_dsi *dsi = host1x_client_to_dsi(client); in tegra_dsi_init() local
723 dsi->output.type = TEGRA_OUTPUT_DSI; in tegra_dsi_init()
724 dsi->output.dev = client->dev; in tegra_dsi_init()
725 dsi->output.ops = &dsi_ops; in tegra_dsi_init()
727 err = tegra_output_init(drm, &dsi->output); in tegra_dsi_init()
734 err = tegra_dsi_debugfs_init(dsi, drm->primary); in tegra_dsi_init()
736 dev_err(dsi->dev, "debugfs setup failed: %d\n", err); in tegra_dsi_init()
739 err = tegra_dsi_pad_calibrate(dsi); in tegra_dsi_init()
741 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); in tegra_dsi_init()
750 struct tegra_dsi *dsi = host1x_client_to_dsi(client); in tegra_dsi_exit() local
754 err = tegra_dsi_debugfs_exit(dsi); in tegra_dsi_exit()
756 dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err); in tegra_dsi_exit()
759 err = tegra_output_disable(&dsi->output); in tegra_dsi_exit()
765 err = tegra_output_exit(&dsi->output); in tegra_dsi_exit()
779 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) in tegra_dsi_setup_clocks() argument
784 parent = clk_get_parent(dsi->clk); in tegra_dsi_setup_clocks()
788 err = clk_set_parent(parent, dsi->clk_parent); in tegra_dsi_setup_clocks()
798 struct tegra_dsi *dsi = host_to_tegra(host); in tegra_dsi_host_attach() local
799 struct tegra_output *output = &dsi->output; in tegra_dsi_host_attach()
801 dsi->flags = device->mode_flags; in tegra_dsi_host_attach()
802 dsi->format = device->format; in tegra_dsi_host_attach()
803 dsi->lanes = device->lanes; in tegra_dsi_host_attach()
817 struct tegra_dsi *dsi = host_to_tegra(host); in tegra_dsi_host_detach() local
818 struct tegra_output *output = &dsi->output; in tegra_dsi_host_detach()
837 struct tegra_dsi *dsi; in tegra_dsi_probe() local
841 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); in tegra_dsi_probe()
842 if (!dsi) in tegra_dsi_probe()
845 dsi->output.dev = dsi->dev = &pdev->dev; in tegra_dsi_probe()
847 err = tegra_output_probe(&dsi->output); in tegra_dsi_probe()
856 dsi->flags = MIPI_DSI_MODE_VIDEO; in tegra_dsi_probe()
857 dsi->format = MIPI_DSI_FMT_RGB888; in tegra_dsi_probe()
858 dsi->lanes = 4; in tegra_dsi_probe()
860 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); in tegra_dsi_probe()
861 if (IS_ERR(dsi->rst)) in tegra_dsi_probe()
862 return PTR_ERR(dsi->rst); in tegra_dsi_probe()
864 dsi->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dsi_probe()
865 if (IS_ERR(dsi->clk)) { in tegra_dsi_probe()
867 return PTR_ERR(dsi->clk); in tegra_dsi_probe()
870 err = clk_prepare_enable(dsi->clk); in tegra_dsi_probe()
876 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); in tegra_dsi_probe()
877 if (IS_ERR(dsi->clk_lp)) { in tegra_dsi_probe()
879 return PTR_ERR(dsi->clk_lp); in tegra_dsi_probe()
882 err = clk_prepare_enable(dsi->clk_lp); in tegra_dsi_probe()
888 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_dsi_probe()
889 if (IS_ERR(dsi->clk_parent)) { in tegra_dsi_probe()
891 return PTR_ERR(dsi->clk_parent); in tegra_dsi_probe()
894 err = clk_prepare_enable(dsi->clk_parent); in tegra_dsi_probe()
900 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); in tegra_dsi_probe()
901 if (IS_ERR(dsi->vdd)) { in tegra_dsi_probe()
903 return PTR_ERR(dsi->vdd); in tegra_dsi_probe()
906 err = regulator_enable(dsi->vdd); in tegra_dsi_probe()
912 err = tegra_dsi_setup_clocks(dsi); in tegra_dsi_probe()
919 dsi->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_dsi_probe()
920 if (IS_ERR(dsi->regs)) in tegra_dsi_probe()
921 return PTR_ERR(dsi->regs); in tegra_dsi_probe()
923 dsi->mipi = tegra_mipi_request(&pdev->dev); in tegra_dsi_probe()
924 if (IS_ERR(dsi->mipi)) in tegra_dsi_probe()
925 return PTR_ERR(dsi->mipi); in tegra_dsi_probe()
927 dsi->host.ops = &tegra_dsi_host_ops; in tegra_dsi_probe()
928 dsi->host.dev = &pdev->dev; in tegra_dsi_probe()
930 err = mipi_dsi_host_register(&dsi->host); in tegra_dsi_probe()
936 INIT_LIST_HEAD(&dsi->client.list); in tegra_dsi_probe()
937 dsi->client.ops = &dsi_client_ops; in tegra_dsi_probe()
938 dsi->client.dev = &pdev->dev; in tegra_dsi_probe()
940 err = host1x_client_register(&dsi->client); in tegra_dsi_probe()
947 platform_set_drvdata(pdev, dsi); in tegra_dsi_probe()
954 struct tegra_dsi *dsi = platform_get_drvdata(pdev); in tegra_dsi_remove() local
957 err = host1x_client_unregister(&dsi->client); in tegra_dsi_remove()
964 mipi_dsi_host_unregister(&dsi->host); in tegra_dsi_remove()
965 tegra_mipi_free(dsi->mipi); in tegra_dsi_remove()
967 regulator_disable(dsi->vdd); in tegra_dsi_remove()
968 clk_disable_unprepare(dsi->clk_parent); in tegra_dsi_remove()
969 clk_disable_unprepare(dsi->clk_lp); in tegra_dsi_remove()
970 clk_disable_unprepare(dsi->clk); in tegra_dsi_remove()
971 reset_control_assert(dsi->rst); in tegra_dsi_remove()
973 err = tegra_output_remove(&dsi->output); in tegra_dsi_remove()