Lines Matching refs:ipu
37 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) in ipu_cm_read() argument
39 return readl(ipu->cm_reg + offset); in ipu_cm_read()
42 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) in ipu_cm_write() argument
44 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
47 void ipu_srm_dp_sync_update(struct ipu_soc *ipu) in ipu_srm_dp_sync_update() argument
51 val = ipu_cm_read(ipu, IPU_SRM_PRI2); in ipu_srm_dp_sync_update()
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2); in ipu_srm_dp_sync_update()
244 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) in ipu_idmac_get() argument
248 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
253 mutex_lock(&ipu->channel_lock); in ipu_idmac_get()
255 channel = &ipu->channel[num]; in ipu_idmac_get()
266 mutex_unlock(&ipu->channel_lock); in ipu_idmac_get()
274 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_put() local
276 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); in ipu_idmac_put()
278 mutex_lock(&ipu->channel_lock); in ipu_idmac_put()
282 mutex_unlock(&ipu->channel_lock); in ipu_idmac_put()
301 struct ipu_soc *ipu = channel->ipu; in __ipu_idmac_reset_current_buffer() local
304 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); in __ipu_idmac_reset_current_buffer()
310 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_set_double_buffer() local
314 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
316 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
321 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
325 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
355 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_lock_enable() local
385 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_lock_enable()
387 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
390 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
392 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_lock_enable()
398 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) in ipu_module_enable() argument
403 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_enable()
405 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_enable()
412 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_enable()
414 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_enable()
416 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_enable()
418 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_enable()
424 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) in ipu_module_disable() argument
429 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_disable()
431 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_disable()
433 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_disable()
435 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_disable()
442 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_disable()
444 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_disable()
452 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_get_current_buffer() local
455 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; in ipu_idmac_get_current_buffer()
461 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_buffer_is_ready() local
465 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
468 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
471 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
474 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
477 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
485 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_select_buffer() local
489 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_select_buffer()
493 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_select_buffer()
495 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_select_buffer()
497 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_select_buffer()
503 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_clear_buffer() local
507 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_clear_buffer()
509 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ in ipu_idmac_clear_buffer()
512 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_clear_buffer()
515 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_clear_buffer()
518 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); in ipu_idmac_clear_buffer()
523 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_clear_buffer()
525 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_clear_buffer()
531 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_channel() local
535 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_channel()
537 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
539 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
541 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_channel()
547 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) in ipu_idmac_channel_busy() argument
549 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); in ipu_idmac_channel_busy()
555 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_wait_busy() local
559 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & in ipu_idmac_wait_busy()
570 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms) in ipu_wait_interrupt() argument
575 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32)); in ipu_wait_interrupt()
576 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) { in ipu_wait_interrupt()
588 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_disable_channel() local
592 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_disable_channel()
595 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
597 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
602 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ in ipu_idmac_disable_channel()
604 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & in ipu_idmac_disable_channel()
606 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
610 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & in ipu_idmac_disable_channel()
612 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
616 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_disable_channel()
619 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
621 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
623 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_disable_channel()
637 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_watermark() local
641 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_watermark()
643 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
648 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
650 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_watermark()
654 static int ipu_memory_reset(struct ipu_soc *ipu) in ipu_memory_reset() argument
658 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); in ipu_memory_reset()
661 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { in ipu_memory_reset()
674 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) in ipu_set_csi_src_mux() argument
682 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_csi_src_mux()
684 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_csi_src_mux()
689 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_csi_src_mux()
691 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_csi_src_mux()
698 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) in ipu_set_ic_src_mux() argument
703 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_ic_src_mux()
705 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_ic_src_mux()
715 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_ic_src_mux()
717 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_ic_src_mux()
793 static int ipu_submodules_init(struct ipu_soc *ipu, in ipu_submodules_init() argument
800 const struct ipu_devtype *devtype = ipu->devtype; in ipu_submodules_init()
802 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); in ipu_submodules_init()
808 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, in ipu_submodules_init()
815 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, in ipu_submodules_init()
822 ret = ipu_ic_init(ipu, dev, in ipu_submodules_init()
830 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, in ipu_submodules_init()
837 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, in ipu_submodules_init()
844 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + in ipu_submodules_init()
851 ret = ipu_dmfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
858 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); in ipu_submodules_init()
864 ret = ipu_smfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
874 ipu_dp_exit(ipu); in ipu_submodules_init()
876 ipu_dmfc_exit(ipu); in ipu_submodules_init()
878 ipu_dc_exit(ipu); in ipu_submodules_init()
880 ipu_di_exit(ipu, 1); in ipu_submodules_init()
882 ipu_di_exit(ipu, 0); in ipu_submodules_init()
884 ipu_ic_exit(ipu); in ipu_submodules_init()
886 ipu_csi_exit(ipu, 1); in ipu_submodules_init()
888 ipu_csi_exit(ipu, 0); in ipu_submodules_init()
890 ipu_cpmem_exit(ipu); in ipu_submodules_init()
896 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) in ipu_irq_handle() argument
903 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); in ipu_irq_handle()
904 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); in ipu_irq_handle()
907 irq = irq_linear_revmap(ipu->domain, in ipu_irq_handle()
917 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_irq_handler() local
923 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_irq_handler()
930 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_err_irq_handler() local
936 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_err_irq_handler()
941 int ipu_map_irq(struct ipu_soc *ipu, int irq) in ipu_map_irq() argument
945 virq = irq_linear_revmap(ipu->domain, irq); in ipu_map_irq()
947 virq = irq_create_mapping(ipu->domain, irq); in ipu_map_irq()
953 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, in ipu_idmac_channel_irq() argument
956 return ipu_map_irq(ipu, irq_type + channel->num); in ipu_idmac_channel_irq()
960 static void ipu_submodules_exit(struct ipu_soc *ipu) in ipu_submodules_exit() argument
962 ipu_smfc_exit(ipu); in ipu_submodules_exit()
963 ipu_dp_exit(ipu); in ipu_submodules_exit()
964 ipu_dmfc_exit(ipu); in ipu_submodules_exit()
965 ipu_dc_exit(ipu); in ipu_submodules_exit()
966 ipu_di_exit(ipu, 1); in ipu_submodules_exit()
967 ipu_di_exit(ipu, 0); in ipu_submodules_exit()
968 ipu_ic_exit(ipu); in ipu_submodules_exit()
969 ipu_csi_exit(ipu, 1); in ipu_submodules_exit()
970 ipu_csi_exit(ipu, 0); in ipu_submodules_exit()
971 ipu_cpmem_exit(ipu); in ipu_submodules_exit()
1035 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) in ipu_add_client_devices() argument
1037 struct device *dev = ipu->dev; in ipu_add_client_devices()
1054 res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset; in ipu_add_client_devices()
1078 static int ipu_irq_init(struct ipu_soc *ipu) in ipu_irq_init() argument
1094 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, in ipu_irq_init()
1095 &irq_generic_chip_ops, ipu); in ipu_irq_init()
1096 if (!ipu->domain) { in ipu_irq_init()
1097 dev_err(ipu->dev, "failed to add irq domain\n"); in ipu_irq_init()
1101 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", in ipu_irq_init()
1105 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); in ipu_irq_init()
1106 irq_domain_remove(ipu->domain); in ipu_irq_init()
1111 gc = irq_get_domain_generic_chip(ipu->domain, i); in ipu_irq_init()
1112 gc->reg_base = ipu->cm_reg; in ipu_irq_init()
1122 irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler); in ipu_irq_init()
1123 irq_set_handler_data(ipu->irq_sync, ipu); in ipu_irq_init()
1124 irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler); in ipu_irq_init()
1125 irq_set_handler_data(ipu->irq_err, ipu); in ipu_irq_init()
1130 static void ipu_irq_exit(struct ipu_soc *ipu) in ipu_irq_exit() argument
1134 irq_set_chained_handler(ipu->irq_err, NULL); in ipu_irq_exit()
1135 irq_set_handler_data(ipu->irq_err, NULL); in ipu_irq_exit()
1136 irq_set_chained_handler(ipu->irq_sync, NULL); in ipu_irq_exit()
1137 irq_set_handler_data(ipu->irq_sync, NULL); in ipu_irq_exit()
1142 irq = irq_linear_revmap(ipu->domain, i); in ipu_irq_exit()
1147 irq_domain_remove(ipu->domain); in ipu_irq_exit()
1150 void ipu_dump(struct ipu_soc *ipu) in ipu_dump() argument
1154 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", in ipu_dump()
1155 ipu_cm_read(ipu, IPU_CONF)); in ipu_dump()
1156 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", in ipu_dump()
1157 ipu_idmac_read(ipu, IDMAC_CONF)); in ipu_dump()
1158 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", in ipu_dump()
1159 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); in ipu_dump()
1160 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", in ipu_dump()
1161 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); in ipu_dump()
1162 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", in ipu_dump()
1163 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); in ipu_dump()
1164 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", in ipu_dump()
1165 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); in ipu_dump()
1166 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", in ipu_dump()
1167 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); in ipu_dump()
1168 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", in ipu_dump()
1169 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); in ipu_dump()
1170 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", in ipu_dump()
1171 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); in ipu_dump()
1172 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", in ipu_dump()
1173 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); in ipu_dump()
1174 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", in ipu_dump()
1175 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); in ipu_dump()
1176 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", in ipu_dump()
1177 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); in ipu_dump()
1178 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", in ipu_dump()
1179 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); in ipu_dump()
1180 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", in ipu_dump()
1181 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); in ipu_dump()
1183 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, in ipu_dump()
1184 ipu_cm_read(ipu, IPU_INT_CTRL(i))); in ipu_dump()
1192 struct ipu_soc *ipu; in ipu_probe() local
1212 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); in ipu_probe()
1213 if (!ipu) in ipu_probe()
1217 ipu->channel[i].ipu = ipu; in ipu_probe()
1218 ipu->devtype = devtype; in ipu_probe()
1219 ipu->ipu_type = devtype->type; in ipu_probe()
1221 spin_lock_init(&ipu->lock); in ipu_probe()
1222 mutex_init(&ipu->channel_lock); in ipu_probe()
1253 ipu->cm_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1255 ipu->idmac_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1259 if (!ipu->cm_reg || !ipu->idmac_reg) in ipu_probe()
1262 ipu->clk = devm_clk_get(&pdev->dev, "bus"); in ipu_probe()
1263 if (IS_ERR(ipu->clk)) { in ipu_probe()
1264 ret = PTR_ERR(ipu->clk); in ipu_probe()
1269 platform_set_drvdata(pdev, ipu); in ipu_probe()
1271 ret = clk_prepare_enable(ipu->clk); in ipu_probe()
1277 ipu->dev = &pdev->dev; in ipu_probe()
1278 ipu->irq_sync = irq_sync; in ipu_probe()
1279 ipu->irq_err = irq_err; in ipu_probe()
1281 ret = ipu_irq_init(ipu); in ipu_probe()
1290 ret = ipu_memory_reset(ipu); in ipu_probe()
1295 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), in ipu_probe()
1298 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); in ipu_probe()
1302 ret = ipu_add_client_devices(ipu, ipu_base); in ipu_probe()
1314 ipu_submodules_exit(ipu); in ipu_probe()
1317 ipu_irq_exit(ipu); in ipu_probe()
1319 clk_disable_unprepare(ipu->clk); in ipu_probe()
1325 struct ipu_soc *ipu = platform_get_drvdata(pdev); in ipu_remove() local
1328 ipu_submodules_exit(ipu); in ipu_remove()
1329 ipu_irq_exit(ipu); in ipu_remove()
1331 clk_disable_unprepare(ipu->clk); in ipu_remove()