Lines Matching refs:st
68 static int adf4350_sync_config(struct adf4350_state *st) in adf4350_sync_config() argument
73 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
83 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
84 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
87 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
88 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
89 i, (u32)st->regs[i] | i); in adf4350_sync_config()
99 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_reg_access() local
107 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); in adf4350_reg_access()
108 ret = adf4350_sync_config(st); in adf4350_reg_access()
110 *readval = st->regs_hw[reg]; in adf4350_reg_access()
118 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt) in adf4350_tune_r_cnt() argument
120 struct adf4350_platform_data *pdata = st->pdata; in adf4350_tune_r_cnt()
124 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) / in adf4350_tune_r_cnt()
126 } while (st->fpfd > ADF4350_MAX_FREQ_PFD); in adf4350_tune_r_cnt()
131 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) in adf4350_set_freq() argument
133 struct adf4350_platform_data *pdata = st->pdata; in adf4350_set_freq()
139 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) in adf4350_set_freq()
150 st->r4_rf_div_sel = 0; in adf4350_set_freq()
154 st->r4_rf_div_sel++; in adf4350_set_freq()
164 chspc = st->chspc; in adf4350_set_freq()
169 r_cnt = adf4350_tune_r_cnt(st, r_cnt); in adf4350_set_freq()
170 st->r1_mod = st->fpfd / chspc; in adf4350_set_freq()
176 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt); in adf4350_set_freq()
179 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); in adf4350_set_freq()
180 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ in adf4350_set_freq()
181 st->r0_fract = do_div(tmp, st->r1_mod); in adf4350_set_freq()
182 st->r0_int = tmp; in adf4350_set_freq()
183 } while (mdiv > st->r0_int); in adf4350_set_freq()
185 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK); in adf4350_set_freq()
187 if (st->r0_fract && st->r1_mod) { in adf4350_set_freq()
188 div_gcd = gcd(st->r1_mod, st->r0_fract); in adf4350_set_freq()
189 st->r1_mod /= div_gcd; in adf4350_set_freq()
190 st->r0_fract /= div_gcd; in adf4350_set_freq()
192 st->r0_fract = 0; in adf4350_set_freq()
193 st->r1_mod = 1; in adf4350_set_freq()
196 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n" in adf4350_set_freq()
199 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod, in adf4350_set_freq()
200 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5", in adf4350_set_freq()
203 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) | in adf4350_set_freq()
204 ADF4350_REG0_FRACT(st->r0_fract); in adf4350_set_freq()
206 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) | in adf4350_set_freq()
207 ADF4350_REG1_MOD(st->r1_mod) | in adf4350_set_freq()
210 st->regs[ADF4350_REG2] = in adf4350_set_freq()
220 st->regs[ADF4350_REG3] = pdata->r3_user_settings & in adf4350_set_freq()
228 st->regs[ADF4350_REG4] = in adf4350_set_freq()
230 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | in adf4350_set_freq()
240 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL; in adf4350_set_freq()
241 st->freq_req = freq; in adf4350_set_freq()
243 return adf4350_sync_config(st); in adf4350_set_freq()
251 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_write() local
263 ret = adf4350_set_freq(st, readin); in adf4350_write()
271 if (st->clk) { in adf4350_write()
272 tmp = clk_round_rate(st->clk, readin); in adf4350_write()
277 ret = clk_set_rate(st->clk, tmp); in adf4350_write()
281 st->clkin = readin; in adf4350_write()
282 ret = adf4350_set_freq(st, st->freq_req); in adf4350_write()
288 st->chspc = readin; in adf4350_write()
292 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; in adf4350_write()
294 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; in adf4350_write()
296 adf4350_sync_config(st); in adf4350_write()
311 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_read() local
318 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * in adf4350_read()
319 (u64)st->fpfd; in adf4350_read()
320 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); in adf4350_read()
322 if (gpio_is_valid(st->pdata->gpio_lock_detect)) in adf4350_read()
323 if (!gpio_get_value(st->pdata->gpio_lock_detect)) { in adf4350_read()
324 dev_dbg(&st->spi->dev, "PLL un-locked\n"); in adf4350_read()
329 if (st->clk) in adf4350_read()
330 st->clkin = clk_get_rate(st->clk); in adf4350_read()
332 val = st->clkin; in adf4350_read()
335 val = st->chspc; in adf4350_read()
338 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); in adf4350_read()
501 struct adf4350_state *st; in adf4350_probe() local
528 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in adf4350_probe()
534 st = iio_priv(indio_dev); in adf4350_probe()
536 st->reg = devm_regulator_get(&spi->dev, "vcc"); in adf4350_probe()
537 if (!IS_ERR(st->reg)) { in adf4350_probe()
538 ret = regulator_enable(st->reg); in adf4350_probe()
544 st->spi = spi; in adf4350_probe()
545 st->pdata = pdata; in adf4350_probe()
556 st->chspc = pdata->channel_spacing; in adf4350_probe()
558 st->clk = clk; in adf4350_probe()
559 st->clkin = clk_get_rate(clk); in adf4350_probe()
561 st->clkin = pdata->clkin; in adf4350_probe()
564 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ? in adf4350_probe()
567 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); in adf4350_probe()
581 ret = adf4350_set_freq(st, pdata->power_up_frequency); in adf4350_probe()
593 if (!IS_ERR(st->reg)) in adf4350_probe()
594 regulator_disable(st->reg); in adf4350_probe()
605 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_remove() local
606 struct regulator *reg = st->reg; in adf4350_remove()
608 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; in adf4350_remove()
609 adf4350_sync_config(st); in adf4350_remove()
613 if (st->clk) in adf4350_remove()
614 clk_disable_unprepare(st->clk); in adf4350_remove()