Lines Matching refs:hfcpci
76 cs->hw.hfcpci.pci_io); in release_io_hfcpci()
77 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcpci()
78 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
83 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
84 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmast… in release_io_hfcpci()
85 del_timer(&cs->hw.hfcpci.timer); in release_io_hfcpci()
86 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, in release_io_hfcpci()
87 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); in release_io_hfcpci()
88 cs->hw.hfcpci.fifos = NULL; in release_io_hfcpci()
89 iounmap((void *)cs->hw.hfcpci.pci_io); in release_io_hfcpci()
99 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped port… in reset_hfcpci()
100 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ in reset_hfcpci()
101 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
104 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable m… in reset_hfcpci()
112 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */ in reset_hfcpci()
113 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in reset_hfcpci()
115 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */ in reset_hfcpci()
116 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in reset_hfcpci()
119 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE; in reset_hfcpci()
120 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */ in reset_hfcpci()
121 cs->hw.hfcpci.bswapped = 0; /* no exchange */ in reset_hfcpci()
122 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */ in reset_hfcpci()
123 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER; in reset_hfcpci()
124 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in reset_hfcpci()
126 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC | in reset_hfcpci()
128 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in reset_hfcpci()
136 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */ in reset_hfcpci()
138 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in reset_hfcpci()
139 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ in reset_hfcpci()
140 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in reset_hfcpci()
141 cs->hw.hfcpci.sctrl_r = 0; in reset_hfcpci()
142 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in reset_hfcpci()
151 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */ in reset_hfcpci()
152 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in reset_hfcpci()
159 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE; in reset_hfcpci()
160 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
170 cs->hw.hfcpci.timer.expires = jiffies + 75; in hfcpci_Timer()
221 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in hfcpci_clear_fifo_rx()
222 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX; in hfcpci_clear_fifo_rx()
224 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1; in hfcpci_clear_fifo_rx()
225 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX; in hfcpci_clear_fifo_rx()
228 cs->hw.hfcpci.fifo_en ^= fifo_state; in hfcpci_clear_fifo_rx()
229 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
230 cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0; in hfcpci_clear_fifo_rx()
236 cs->hw.hfcpci.fifo_en |= fifo_state; in hfcpci_clear_fifo_rx()
237 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
248 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2; in hfcpci_clear_fifo_tx()
249 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX; in hfcpci_clear_fifo_tx()
251 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1; in hfcpci_clear_fifo_tx()
252 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX; in hfcpci_clear_fifo_tx()
255 cs->hw.hfcpci.fifo_en ^= fifo_state; in hfcpci_clear_fifo_tx()
256 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
262 cs->hw.hfcpci.fifo_en |= fifo_state; in hfcpci_clear_fifo_tx()
263 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
339 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx; in receive_dmsg()
461 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) { in main_rec_hfcpci()
462 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in main_rec_hfcpci()
463 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2; in main_rec_hfcpci()
466 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1; in main_rec_hfcpci()
467 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1; in main_rec_hfcpci()
496 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) { in main_rec_hfcpci()
500 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt; in main_rec_hfcpci()
530 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx; in hfcpci_fill_dfifo()
603 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) { in hfcpci_fill_fifo()
604 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2; in hfcpci_fill_fifo()
605 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2; in hfcpci_fill_fifo()
607 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1; in hfcpci_fill_fifo()
608 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1; in hfcpci_fill_fifo()
775 …(!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_… in hfcpci_auxcmd()
780 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT; in hfcpci_auxcmd()
781 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */ in hfcpci_auxcmd()
786 cs->dc.hfcpci.ph_state = 1; in hfcpci_auxcmd()
787 cs->hw.hfcpci.nt_mode = 1; in hfcpci_auxcmd()
788 cs->hw.hfcpci.nt_timer = 0; in hfcpci_auxcmd()
794 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) || in hfcpci_auxcmd()
795 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12)) in hfcpci_auxcmd()
801 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */ in hfcpci_auxcmd()
802 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC; in hfcpci_auxcmd()
803 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX; in hfcpci_auxcmd()
806 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */ in hfcpci_auxcmd()
807 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC; in hfcpci_auxcmd()
808 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX; in hfcpci_auxcmd()
810 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA; in hfcpci_auxcmd()
811 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA; in hfcpci_auxcmd()
812 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */ in hfcpci_auxcmd()
813 cs->hw.hfcpci.ctmt &= ~2; in hfcpci_auxcmd()
814 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in hfcpci_auxcmd()
815 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in hfcpci_auxcmd()
816 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in hfcpci_auxcmd()
817 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in hfcpci_auxcmd()
818 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in hfcpci_auxcmd()
819 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_auxcmd()
820 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_auxcmd()
840 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in receive_emsg()
841 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2; in receive_emsg()
937 if (!(cs->hw.hfcpci.int_m2 & 0x08)) { in hfcpci_interrupt()
938 debugl1(cs, "HFC-PCI: int_m2 %x not initialised", cs->hw.hfcpci.int_m2); in hfcpci_interrupt()
954 val &= cs->hw.hfcpci.int_m1; in hfcpci_interrupt()
958 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state, in hfcpci_interrupt()
960 cs->dc.hfcpci.ph_state = exval; in hfcpci_interrupt()
965 if (cs->hw.hfcpci.nt_mode) { in hfcpci_interrupt()
966 if ((--cs->hw.hfcpci.nt_timer) < 0) in hfcpci_interrupt()
970 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_interrupt()
974 cs->hw.hfcpci.int_s1 |= val; in hfcpci_interrupt()
978 if (cs->hw.hfcpci.int_s1 & 0x18) { in hfcpci_interrupt()
980 val = cs->hw.hfcpci.int_s1; in hfcpci_interrupt()
981 cs->hw.hfcpci.int_s1 = exval; in hfcpci_interrupt()
984 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) { in hfcpci_interrupt()
1000 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) { in hfcpci_interrupt()
1082 if (cs->hw.hfcpci.int_s1 && count--) { in hfcpci_interrupt()
1083 val = cs->hw.hfcpci.int_s1; in hfcpci_interrupt()
1084 cs->hw.hfcpci.int_s1 = 0; in hfcpci_interrupt()
1183 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER; in HFCPCI_l1hw()
1184 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1196 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER; in HFCPCI_l1hw()
1197 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1202 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER; in HFCPCI_l1hw()
1203 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1212 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1; in HFCPCI_l1hw()
1213 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1219 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08; in HFCPCI_l1hw()
1220 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1229 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */ in HFCPCI_l1hw()
1230 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in HFCPCI_l1hw()
1280 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1281 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1285 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */ in mode_hfcpci()
1286 cs->hw.hfcpci.sctrl_e |= 0x80; in mode_hfcpci()
1288 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1289 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1293 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1294 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1300 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA; in mode_hfcpci()
1301 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA; in mode_hfcpci()
1303 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA; in mode_hfcpci()
1304 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA; in mode_hfcpci()
1307 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2; in mode_hfcpci()
1308 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1310 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1; in mode_hfcpci()
1311 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1318 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1319 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1321 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1322 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1325 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2; in mode_hfcpci()
1326 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1327 cs->hw.hfcpci.ctmt |= 2; in mode_hfcpci()
1328 cs->hw.hfcpci.conn &= ~0x18; in mode_hfcpci()
1330 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1; in mode_hfcpci()
1331 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1332 cs->hw.hfcpci.ctmt |= 1; in mode_hfcpci()
1333 cs->hw.hfcpci.conn &= ~0x03; in mode_hfcpci()
1340 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1341 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1343 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1344 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1347 cs->hw.hfcpci.last_bfifo_cnt[1] = 0; in mode_hfcpci()
1348 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2; in mode_hfcpci()
1349 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1350 cs->hw.hfcpci.ctmt &= ~2; in mode_hfcpci()
1351 cs->hw.hfcpci.conn &= ~0x18; in mode_hfcpci()
1353 cs->hw.hfcpci.last_bfifo_cnt[0] = 0; in mode_hfcpci()
1354 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1; in mode_hfcpci()
1355 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1356 cs->hw.hfcpci.ctmt &= ~1; in mode_hfcpci()
1357 cs->hw.hfcpci.conn &= ~0x03; in mode_hfcpci()
1362 cs->hw.hfcpci.conn |= 0x10; in mode_hfcpci()
1363 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1364 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1365 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2; in mode_hfcpci()
1366 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1368 cs->hw.hfcpci.conn |= 0x02; in mode_hfcpci()
1369 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1370 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1371 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1; in mode_hfcpci()
1372 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1376 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); in mode_hfcpci()
1377 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in mode_hfcpci()
1378 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in mode_hfcpci()
1379 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in mode_hfcpci()
1380 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in mode_hfcpci()
1381 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in mode_hfcpci()
1382 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in mode_hfcpci()
1511 if (!cs->hw.hfcpci.nt_mode) in hfcpci_bh()
1512 switch (cs->dc.hfcpci.ph_state) { in hfcpci_bh()
1532 switch (cs->dc.hfcpci.ph_state) { in hfcpci_bh()
1534 if (cs->hw.hfcpci.nt_timer < 0) { in hfcpci_bh()
1535 cs->hw.hfcpci.nt_timer = 0; in hfcpci_bh()
1536 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_bh()
1537 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1543 cs->dc.hfcpci.ph_state = 4; in hfcpci_bh()
1545 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER; in hfcpci_bh()
1546 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1547 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER; in hfcpci_bh()
1548 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125; in hfcpci_bh()
1549 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1550 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1551 cs->hw.hfcpci.nt_timer = NT_T1_COUNT; in hfcpci_bh()
1558 cs->hw.hfcpci.nt_timer = 0; in hfcpci_bh()
1559 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_bh()
1560 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1621 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_card_msg()
1622 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_card_msg()
1624 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in hfcpci_card_msg()
1649 cs->hw.hfcpci.int_s1 = 0; in setup_hfcpci()
1650 cs->dc.hfcpci.ph_state = 0; in setup_hfcpci()
1651 cs->hw.hfcpci.fifo = 255; in setup_hfcpci()
1690 cs->hw.hfcpci.dev = dev_hfcpci; in setup_hfcpci()
1696 cs->hw.hfcpci.pci_io = (char *)(unsigned long)dev_hfcpci->resource[1].start; in setup_hfcpci()
1699 if (!cs->hw.hfcpci.pci_io) { in setup_hfcpci()
1705 cs->hw.hfcpci.fifos = pci_alloc_consistent(cs->hw.hfcpci.dev, in setup_hfcpci()
1706 0x8000, &cs->hw.hfcpci.dma); in setup_hfcpci()
1707 if (!cs->hw.hfcpci.fifos) { in setup_hfcpci()
1711 if (cs->hw.hfcpci.dma & 0x7fff) { in setup_hfcpci()
1714 (u_long)cs->hw.hfcpci.dma); in setup_hfcpci()
1715 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, in setup_hfcpci()
1716 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); in setup_hfcpci()
1719 pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u32)cs->hw.hfcpci.dma); in setup_hfcpci()
1720 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256); in setup_hfcpci()
1723 cs->hw.hfcpci.pci_io, in setup_hfcpci()
1724 cs->hw.hfcpci.fifos, in setup_hfcpci()
1725 (u_long)cs->hw.hfcpci.dma, in setup_hfcpci()
1730 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped port… in setup_hfcpci()
1731 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */ in setup_hfcpci()
1732 cs->hw.hfcpci.int_m1 = 0; in setup_hfcpci()
1733 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in setup_hfcpci()
1734 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in setup_hfcpci()
1749 cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer; in setup_hfcpci()
1750 cs->hw.hfcpci.timer.data = (long) cs; in setup_hfcpci()
1751 init_timer(&cs->hw.hfcpci.timer); in setup_hfcpci()