941 	for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {  in find_and_set_predefined_video_timings()
1003 		const struct v4l2_bt_timings *bt)  in configure_custom_video_timings()  argument
1006 	u32 width = htotal(bt);  in configure_custom_video_timings()
1007 	u32 height = vtotal(bt);  in configure_custom_video_timings()
1008 	u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;  in configure_custom_video_timings()
1009 	u16 cp_start_eav = width - bt->hfrontporch;  in configure_custom_video_timings()
1010 	u16 cp_start_vbi = height - bt->vfrontporch;  in configure_custom_video_timings()
1011 	u16 cp_end_vbi = bt->vsync + bt->vbackporch;  in configure_custom_video_timings()
1012 	u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?  in configure_custom_video_timings()
1013 		((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;  in configure_custom_video_timings()
1157 		if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {  in set_rgb_quantization_range()
1362 	for (i = 0; adv7604_timings[i].bt.height; i++) {  in stdi2dv_timings()
1363 		if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)  in stdi2dv_timings()
1365 		if (adv7604_timings[i].bt.vsync != stdi->lcvs)  in stdi2dv_timings()
1368 		pix_clk = hfreq * htotal(&adv7604_timings[i].bt);  in stdi2dv_timings()
1370 		if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&  in stdi2dv_timings()
1371 		    (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {  in stdi2dv_timings()
1477 	cap->bt.max_width = 1920;  in adv7604_dv_timings_cap()
1478 	cap->bt.max_height = 1200;  in adv7604_dv_timings_cap()
1479 	cap->bt.min_pixelclock = 25000000;  in adv7604_dv_timings_cap()
1486 		cap->bt.max_pixelclock = 225000000;  in adv7604_dv_timings_cap()
1491 		cap->bt.max_pixelclock = 170000000;  in adv7604_dv_timings_cap()
1495 	cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |  in adv7604_dv_timings_cap()
1497 	cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |  in adv7604_dv_timings_cap()
1509 	for (i = 0; adv7604_timings[i].bt.width; i++) {  in adv7604_fill_optional_dv_timings_fields()
1555 	struct v4l2_bt_timings *bt = &timings->bt;  in adv7604_query_dv_timings()  local
1574 	bt->interlaced = stdi.interlaced ?  in adv7604_query_dv_timings()
1581 		bt->width = hdmi_read16(sd, 0x07, 0xfff);  in adv7604_query_dv_timings()
1582 		bt->height = hdmi_read16(sd, 0x09, 0xfff);  in adv7604_query_dv_timings()
1583 		bt->pixelclock = info->read_hdmi_pixelclock(sd);  in adv7604_query_dv_timings()
1584 		bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);  in adv7604_query_dv_timings()
1585 		bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);  in adv7604_query_dv_timings()
1586 		bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);  in adv7604_query_dv_timings()
1587 		bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;  in adv7604_query_dv_timings()
1588 		bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;  in adv7604_query_dv_timings()
1589 		bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;  in adv7604_query_dv_timings()
1590 		bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |  in adv7604_query_dv_timings()
1592 		if (bt->interlaced == V4L2_DV_INTERLACED) {  in adv7604_query_dv_timings()
1593 			bt->height += hdmi_read16(sd, 0x0b, 0xfff);  in adv7604_query_dv_timings()
1594 			bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;  in adv7604_query_dv_timings()
1595 			bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;  in adv7604_query_dv_timings()
1596 			bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;  in adv7604_query_dv_timings()
1647 	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||  in adv7604_query_dv_timings()
1648 			(is_digital_input(sd) && bt->pixelclock > 225000000)) {  in adv7604_query_dv_timings()
1650 				__func__, (u32)bt->pixelclock);  in adv7604_query_dv_timings()
1665 	struct v4l2_bt_timings *bt;  in adv7604_s_dv_timings()  local
1676 	bt = &timings->bt;  in adv7604_s_dv_timings()
1678 	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||  in adv7604_s_dv_timings()
1679 			(is_digital_input(sd) && bt->pixelclock > 225000000)) {  in adv7604_s_dv_timings()
1681 				__func__, (u32)bt->pixelclock);  in adv7604_s_dv_timings()
1689 	cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);  in adv7604_s_dv_timings()
1696 		configure_custom_video_timings(sd, bt);  in adv7604_s_dv_timings()
1828 	format->width = state->timings.bt.width;  in adv7604_fill_format()
1829 	format->height = state->timings.bt.height;  in adv7604_fill_format()
1832 	if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)  in adv7604_fill_format()
1833 		format->colorspace = (state->timings.bt.height <= 576) ?  in adv7604_fill_format()