Lines Matching refs:inter
254 static int netup_fpga_op_rw(struct fpga_internal *inter, int addr, in netup_fpga_op_rw() argument
257 inter->fpga_rw(inter->dev, NETUP_CI_FLG_AD, addr, 0); in netup_fpga_op_rw()
258 return inter->fpga_rw(inter->dev, 0, val, read); in netup_fpga_op_rw()
267 struct fpga_internal *inter = state->internal; in altera_ci_op_cam() local
275 mutex_lock(&inter->fpga_mutex); in altera_ci_op_cam()
277 netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0); in altera_ci_op_cam()
278 netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0); in altera_ci_op_cam()
279 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_op_cam()
284 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0); in altera_ci_op_cam()
285 mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read); in altera_ci_op_cam()
287 mutex_unlock(&inter->fpga_mutex); in altera_ci_op_cam()
325 struct fpga_internal *inter = state->internal; in altera_ci_slot_reset() local
335 mutex_lock(&inter->fpga_mutex); in altera_ci_slot_reset()
337 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_slot_reset()
338 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_reset()
341 mutex_unlock(&inter->fpga_mutex); in altera_ci_slot_reset()
346 mutex_lock(&inter->fpga_mutex); in altera_ci_slot_reset()
348 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_reset()
350 mutex_unlock(&inter->fpga_mutex); in altera_ci_slot_reset()
374 struct fpga_internal *inter = state->internal; in altera_ci_slot_ts_ctl() local
382 mutex_lock(&inter->fpga_mutex); in altera_ci_slot_ts_ctl()
384 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_slot_ts_ctl()
385 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_ts_ctl()
388 mutex_unlock(&inter->fpga_mutex); in altera_ci_slot_ts_ctl()
396 struct fpga_internal *inter = in netup_read_ci_status() local
402 mutex_lock(&inter->fpga_mutex); in netup_read_ci_status()
404 ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD); in netup_read_ci_status()
405 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in netup_read_ci_status()
407 mutex_unlock(&inter->fpga_mutex); in netup_read_ci_status()
409 if (inter->state[1] != NULL) { in netup_read_ci_status()
410 inter->state[1]->status = in netup_read_ci_status()
415 __func__, inter->state[1]->status); in netup_read_ci_status()
418 if (inter->state[0] != NULL) { in netup_read_ci_status()
419 inter->state[0]->status = in netup_read_ci_status()
424 __func__, inter->state[0]->status); in netup_read_ci_status()
432 struct fpga_internal *inter = NULL; in altera_ci_irq() local
439 inter = temp_int->internal; in altera_ci_irq()
440 schedule_work(&inter->work); in altera_ci_irq()
523 struct fpga_internal *inter = pid_filt->internal; in altera_pid_control() local
530 mutex_lock(&inter->fpga_mutex); in altera_pid_control()
532 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0); in altera_pid_control()
533 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1, in altera_pid_control()
536 store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD); in altera_pid_control()
543 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0); in altera_pid_control()
545 mutex_unlock(&inter->fpga_mutex); in altera_pid_control()
554 struct fpga_internal *inter = pid_filt->internal; in altera_toggle_fullts_streaming() local
566 mutex_lock(&inter->fpga_mutex); in altera_toggle_fullts_streaming()
569 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0); in altera_toggle_fullts_streaming()
571 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1, in altera_toggle_fullts_streaming()
574 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, in altera_toggle_fullts_streaming()
578 mutex_unlock(&inter->fpga_mutex); in altera_toggle_fullts_streaming()
585 struct fpga_internal *inter = temp_int->internal; in altera_pid_feed_control() local
586 struct netup_hw_pid_filter *pid_filt = inter->pid_filt[filt_nr - 1]; in altera_pid_feed_control()
641 struct fpga_internal *inter = NULL; in altera_hw_filt_init() local
654 inter = temp_int->internal; in altera_hw_filt_init()
655 (inter->filts_used)++; in altera_hw_filt_init()
658 inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL); in altera_hw_filt_init()
659 if (!inter) { in altera_hw_filt_init()
664 temp_int = append_internal(inter); in altera_hw_filt_init()
665 inter->filts_used = 1; in altera_hw_filt_init()
666 inter->dev = config->dev; in altera_hw_filt_init()
667 inter->fpga_rw = config->fpga_rw; in altera_hw_filt_init()
668 mutex_init(&inter->fpga_mutex); in altera_hw_filt_init()
669 inter->strt_wrk = 1; in altera_hw_filt_init()
675 inter->pid_filt[hw_filt_nr - 1] = pid_filt; in altera_hw_filt_init()
677 pid_filt->internal = inter; in altera_hw_filt_init()
708 struct fpga_internal *inter = NULL; in altera_ci_init() local
722 inter = temp_int->internal; in altera_ci_init()
723 (inter->cis_used)++; in altera_ci_init()
724 inter->fpga_rw = config->fpga_rw; in altera_ci_init()
727 inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL); in altera_ci_init()
728 if (!inter) { in altera_ci_init()
733 temp_int = append_internal(inter); in altera_ci_init()
734 inter->cis_used = 1; in altera_ci_init()
735 inter->dev = config->dev; in altera_ci_init()
736 inter->fpga_rw = config->fpga_rw; in altera_ci_init()
737 mutex_init(&inter->fpga_mutex); in altera_ci_init()
738 inter->strt_wrk = 1; in altera_ci_init()
744 state->internal = inter; in altera_ci_init()
765 inter->state[ci_nr - 1] = state; in altera_ci_init()
769 if (inter->strt_wrk) { in altera_ci_init()
770 INIT_WORK(&inter->work, netup_read_ci_status); in altera_ci_init()
771 inter->strt_wrk = 0; in altera_ci_init()
776 mutex_lock(&inter->fpga_mutex); in altera_ci_init()
779 netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0); in altera_ci_init()
780 netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0); in altera_ci_init()
783 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); in altera_ci_init()
785 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_init()
787 ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD); in altera_ci_init()
789 netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0); in altera_ci_init()
791 mutex_unlock(&inter->fpga_mutex); in altera_ci_init()
795 schedule_work(&inter->work); in altera_ci_init()
810 struct fpga_internal *inter = NULL; in altera_ci_tuner_reset() local
821 inter = temp_int->internal; in altera_ci_tuner_reset()
823 mutex_lock(&inter->fpga_mutex); in altera_ci_tuner_reset()
825 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); in altera_ci_tuner_reset()
827 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_tuner_reset()
830 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_tuner_reset()
832 mutex_unlock(&inter->fpga_mutex); in altera_ci_tuner_reset()