63 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val)  in reg_write()  function
106 	return reg_write(state, 0x03, state->regs[0x03]);  in qm1d1c0042_set_srch_mode()
116 	ret = reg_write(state, 0x01, state->regs[0x01]);  in qm1d1c0042_wakeup()
118 		ret = reg_write(state, 0x05, state->regs[0x05]);  in qm1d1c0042_wakeup()
204 	ret = reg_write(state, 0x02, val);  in qm1d1c0042_set_params()
212 	ret = reg_write(state, 0x06, state->regs[0x06]);  in qm1d1c0042_set_params()
218 	ret = reg_write(state, 0x07, state->regs[0x07]);  in qm1d1c0042_set_params()
229 	ret = reg_write(state, 0x08, val);  in qm1d1c0042_set_params()
250 	ret = reg_write(state, 0x09, state->regs[0x09]);  in qm1d1c0042_set_params()
252 		ret = reg_write(state, 0x0a, state->regs[0x0a]);  in qm1d1c0042_set_params()
254 		ret = reg_write(state, 0x0b, state->regs[0x0b]);  in qm1d1c0042_set_params()
260 		ret = reg_write(state, 0x13, state->regs[0x13]);  in qm1d1c0042_set_params()
268 	ret = reg_write(state, 0x0c, val);  in qm1d1c0042_set_params()
273 	ret = reg_write(state, 0x0c, val);  in qm1d1c0042_set_params()
286 		ret = reg_write(state, 0x08, 0x09);  in qm1d1c0042_set_params()
291 		ret = reg_write(state, 0x13, state->regs[0x13]);  in qm1d1c0042_set_params()
307 	ret = reg_write(state, 0x05, state->regs[0x05]);  in qm1d1c0042_sleep()
309 		ret = reg_write(state, 0x01, state->regs[0x01]);  in qm1d1c0042_sleep()
325 	reg_write(state, 0x01, 0x0c);  in qm1d1c0042_init()
326 	reg_write(state, 0x01, 0x0c);  in qm1d1c0042_init()
328 	ret = reg_write(state, 0x01, 0x0c); /* soft reset on */  in qm1d1c0042_init()
334 	ret = reg_write(state, 0x01, val); /* soft reset off */  in qm1d1c0042_init()
345 	ret = reg_write(state, 0x0c, state->regs[0x0c]);  in qm1d1c0042_init()
352 		ret = reg_write(state, i, state->regs[i]);  in qm1d1c0042_init()
357 		ret = reg_write(state, i, state->regs[i]);  in qm1d1c0042_init()