Lines Matching refs:asic
92 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value) in asic3_write_register() argument
94 iowrite16(value, asic->mapping + in asic3_write_register()
95 (reg >> asic->bus_shift)); in asic3_write_register()
99 u32 asic3_read_register(struct asic3 *asic, unsigned int reg) in asic3_read_register() argument
101 return ioread16(asic->mapping + in asic3_read_register()
102 (reg >> asic->bus_shift)); in asic3_read_register()
106 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) in asic3_set_register() argument
111 spin_lock_irqsave(&asic->lock, flags); in asic3_set_register()
112 val = asic3_read_register(asic, reg); in asic3_set_register()
117 asic3_write_register(asic, reg, val); in asic3_set_register()
118 spin_unlock_irqrestore(&asic->lock, flags); in asic3_set_register()
126 static void asic3_irq_flip_edge(struct asic3 *asic, in asic3_irq_flip_edge() argument
132 spin_lock_irqsave(&asic->lock, flags); in asic3_irq_flip_edge()
133 edge = asic3_read_register(asic, in asic3_irq_flip_edge()
136 asic3_write_register(asic, in asic3_irq_flip_edge()
138 spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_flip_edge()
143 struct asic3 *asic = irq_desc_get_handler_data(desc); in asic3_irq_demux() local
154 spin_lock_irqsave(&asic->lock, flags); in asic3_irq_demux()
155 status = asic3_read_register(asic, in asic3_irq_demux()
157 spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_demux()
171 spin_lock_irqsave(&asic->lock, flags); in asic3_irq_demux()
172 istat = asic3_read_register(asic, in asic3_irq_demux()
176 asic3_write_register(asic, in asic3_irq_demux()
179 spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_demux()
188 irqnr = asic->irq_base + in asic3_irq_demux()
192 if (asic->irq_bothedge[bank] & bit) in asic3_irq_demux()
193 asic3_irq_flip_edge(asic, base, in asic3_irq_demux()
203 generic_handle_irq(asic->irq_base + i); in asic3_irq_demux()
208 dev_err(asic->dev, "interrupt processing overrun\n"); in asic3_irq_demux()
211 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) in asic3_irq_to_bank() argument
215 n = (irq - asic->irq_base) >> 4; in asic3_irq_to_bank()
220 static inline int asic3_irq_to_index(struct asic3 *asic, int irq) in asic3_irq_to_index() argument
222 return (irq - asic->irq_base) & 0xf; in asic3_irq_to_index()
227 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_mask_gpio_irq() local
231 bank = asic3_irq_to_bank(asic, data->irq); in asic3_mask_gpio_irq()
232 index = asic3_irq_to_index(asic, data->irq); in asic3_mask_gpio_irq()
234 spin_lock_irqsave(&asic->lock, flags); in asic3_mask_gpio_irq()
235 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); in asic3_mask_gpio_irq()
237 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); in asic3_mask_gpio_irq()
238 spin_unlock_irqrestore(&asic->lock, flags); in asic3_mask_gpio_irq()
243 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_mask_irq() local
247 spin_lock_irqsave(&asic->lock, flags); in asic3_mask_irq()
248 regval = asic3_read_register(asic, in asic3_mask_irq()
253 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); in asic3_mask_irq()
255 asic3_write_register(asic, in asic3_mask_irq()
259 spin_unlock_irqrestore(&asic->lock, flags); in asic3_mask_irq()
264 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_unmask_gpio_irq() local
268 bank = asic3_irq_to_bank(asic, data->irq); in asic3_unmask_gpio_irq()
269 index = asic3_irq_to_index(asic, data->irq); in asic3_unmask_gpio_irq()
271 spin_lock_irqsave(&asic->lock, flags); in asic3_unmask_gpio_irq()
272 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); in asic3_unmask_gpio_irq()
274 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); in asic3_unmask_gpio_irq()
275 spin_unlock_irqrestore(&asic->lock, flags); in asic3_unmask_gpio_irq()
280 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_unmask_irq() local
284 spin_lock_irqsave(&asic->lock, flags); in asic3_unmask_irq()
285 regval = asic3_read_register(asic, in asic3_unmask_irq()
290 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); in asic3_unmask_irq()
292 asic3_write_register(asic, in asic3_unmask_irq()
296 spin_unlock_irqrestore(&asic->lock, flags); in asic3_unmask_irq()
301 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_gpio_irq_type() local
306 bank = asic3_irq_to_bank(asic, data->irq); in asic3_gpio_irq_type()
307 index = asic3_irq_to_index(asic, data->irq); in asic3_gpio_irq_type()
310 spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_irq_type()
311 level = asic3_read_register(asic, in asic3_gpio_irq_type()
313 edge = asic3_read_register(asic, in asic3_gpio_irq_type()
315 trigger = asic3_read_register(asic, in asic3_gpio_irq_type()
317 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit; in asic3_gpio_irq_type()
327 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base)) in asic3_gpio_irq_type()
331 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit; in asic3_gpio_irq_type()
344 dev_notice(asic->dev, "irq type not changed\n"); in asic3_gpio_irq_type()
346 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, in asic3_gpio_irq_type()
348 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, in asic3_gpio_irq_type()
350 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, in asic3_gpio_irq_type()
352 spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_irq_type()
358 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_gpio_irq_set_wake() local
362 bank = asic3_irq_to_bank(asic, data->irq); in asic3_gpio_irq_set_wake()
363 index = asic3_irq_to_index(asic, data->irq); in asic3_gpio_irq_set_wake()
366 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on); in asic3_gpio_irq_set_wake()
389 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_irq_probe() local
397 asic->irq_nr = ret; in asic3_irq_probe()
401 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), in asic3_irq_probe()
404 irq_base = asic->irq_base; in asic3_irq_probe()
407 if (irq < asic->irq_base + ASIC3_NUM_GPIOS) in asic3_irq_probe()
412 irq_set_chip_data(irq, asic); in asic3_irq_probe()
417 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK), in asic3_irq_probe()
420 irq_set_chained_handler(asic->irq_nr, asic3_irq_demux); in asic3_irq_probe()
421 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); in asic3_irq_probe()
422 irq_set_handler_data(asic->irq_nr, asic); in asic3_irq_probe()
429 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_irq_remove() local
432 irq_base = asic->irq_base; in asic3_irq_remove()
439 irq_set_chained_handler(asic->irq_nr, NULL); in asic3_irq_remove()
449 struct asic3 *asic; in asic3_gpio_direction() local
451 asic = container_of(chip, struct asic3, gpio); in asic3_gpio_direction()
455 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_direction()
460 spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_direction()
462 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); in asic3_gpio_direction()
470 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg); in asic3_gpio_direction()
472 spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_direction()
495 struct asic3 *asic; in asic3_gpio_get() local
497 asic = container_of(chip, struct asic3, gpio); in asic3_gpio_get()
501 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_get()
506 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask; in asic3_gpio_get()
515 struct asic3 *asic; in asic3_gpio_set() local
517 asic = container_of(chip, struct asic3, gpio); in asic3_gpio_set()
521 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_set()
528 spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_set()
530 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); in asic3_gpio_set()
537 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg); in asic3_gpio_set()
539 spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_set()
546 struct asic3 *asic = container_of(chip, struct asic3, gpio); in asic3_gpio_to_irq() local
548 return asic->irq_base + offset; in asic3_gpio_to_irq()
554 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_gpio_probe() local
565 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); in asic3_gpio_probe()
566 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); in asic3_gpio_probe()
567 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); in asic3_gpio_probe()
568 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); in asic3_gpio_probe()
588 asic3_write_register(asic, in asic3_gpio_probe()
592 asic3_write_register(asic, in asic3_gpio_probe()
595 asic3_write_register(asic, in asic3_gpio_probe()
601 return gpiochip_add(&asic->gpio); in asic3_gpio_probe()
606 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_gpio_remove() local
608 gpiochip_remove(&asic->gpio); in asic3_gpio_remove()
612 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) in asic3_clk_enable() argument
617 spin_lock_irqsave(&asic->lock, flags); in asic3_clk_enable()
619 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_enable()
621 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); in asic3_clk_enable()
623 spin_unlock_irqrestore(&asic->lock, flags); in asic3_clk_enable()
626 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk) in asic3_clk_disable() argument
633 spin_lock_irqsave(&asic->lock, flags); in asic3_clk_disable()
635 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_disable()
637 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); in asic3_clk_disable()
639 spin_unlock_irqrestore(&asic->lock, flags); in asic3_clk_disable()
663 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in ds1wm_enable() local
666 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_enable()
667 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_enable()
668 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_enable()
672 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), in ds1wm_enable()
675 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), in ds1wm_enable()
678 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in ds1wm_enable()
687 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in ds1wm_disable() local
689 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in ds1wm_disable()
692 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_disable()
693 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_disable()
694 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_disable()
711 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_pwr() local
713 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state); in asic3_mmc_pwr()
718 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_clk_div() local
720 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state); in asic3_mmc_clk_div()
744 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_enable() local
747 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
749 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
751 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
753 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
756 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_enable()
760 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_enable()
764 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), in asic3_mmc_enable()
767 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_enable()
768 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); in asic3_mmc_enable()
771 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_mmc_enable()
775 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
779 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift, in asic3_mmc_enable()
787 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_disable() local
790 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_disable()
794 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_disable()
795 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); in asic3_mmc_disable()
796 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_disable()
797 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_disable()
822 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_enable() local
824 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_enable()
832 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_disable() local
834 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_disable()
842 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_suspend() local
844 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0) in asic3_leds_suspend()
847 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_suspend()
883 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_mfd_probe() local
889 dev_dbg(asic->dev, "no SDIO MEM resource\n"); in asic3_mfd_probe()
893 dev_dbg(asic->dev, "no SDIO IRQ resource\n"); in asic3_mfd_probe()
896 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_mfd_probe()
899 ds1wm_resources[0].start >>= asic->bus_shift; in asic3_mfd_probe()
900 ds1wm_resources[0].end >>= asic->bus_shift; in asic3_mfd_probe()
904 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) + in asic3_mfd_probe()
906 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift); in asic3_mfd_probe()
907 if (!asic->tmio_cnf) { in asic3_mfd_probe()
909 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n"); in asic3_mfd_probe()
913 asic3_mmc_resources[0].start >>= asic->bus_shift; in asic3_mfd_probe()
914 asic3_mmc_resources[0].end >>= asic->bus_shift; in asic3_mfd_probe()
919 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL); in asic3_mfd_probe()
949 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_mfd_remove() local
952 iounmap(asic->tmio_cnf); in asic3_mfd_remove()
959 struct asic3 *asic; in asic3_probe() local
964 asic = devm_kzalloc(&pdev->dev, in asic3_probe()
966 if (asic == NULL) { in asic3_probe()
971 spin_lock_init(&asic->lock); in asic3_probe()
972 platform_set_drvdata(pdev, asic); in asic3_probe()
973 asic->dev = &pdev->dev; in asic3_probe()
977 dev_err(asic->dev, "no MEM resource\n"); in asic3_probe()
981 asic->mapping = ioremap(mem->start, resource_size(mem)); in asic3_probe()
982 if (!asic->mapping) { in asic3_probe()
983 dev_err(asic->dev, "Couldn't ioremap\n"); in asic3_probe()
987 asic->irq_base = pdata->irq_base; in asic3_probe()
990 asic->bus_shift = 2 - (resource_size(mem) >> 12); in asic3_probe()
993 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
997 dev_err(asic->dev, "Couldn't probe IRQs\n"); in asic3_probe()
1001 asic->gpio.label = "asic3"; in asic3_probe()
1002 asic->gpio.base = pdata->gpio_base; in asic3_probe()
1003 asic->gpio.ngpio = ASIC3_NUM_GPIOS; in asic3_probe()
1004 asic->gpio.get = asic3_gpio_get; in asic3_probe()
1005 asic->gpio.set = asic3_gpio_set; in asic3_probe()
1006 asic->gpio.direction_input = asic3_gpio_direction_input; in asic3_probe()
1007 asic->gpio.direction_output = asic3_gpio_direction_output; in asic3_probe()
1008 asic->gpio.to_irq = asic3_gpio_to_irq; in asic3_probe()
1014 dev_err(asic->dev, "GPIO probe failed\n"); in asic3_probe()
1021 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); in asic3_probe()
1025 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_probe()
1028 dev_info(asic->dev, "ASIC3 Core driver\n"); in asic3_probe()
1036 iounmap(asic->mapping); in asic3_probe()
1044 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_remove() local
1046 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_remove()
1056 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); in asic3_remove()
1058 iounmap(asic->mapping); in asic3_remove()