Lines Matching refs:reg_offset

203 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
204 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
205 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
207 	{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
208 	{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
209 	{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
210 	{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
211 	{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
213 	{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
214 	{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
215 	{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
216 	{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
231 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
232 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
233 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
234 	{ .reg_offset = 0, .mask = MAX77836_INT1_ADC1K_MASK, },
236 	{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
237 	{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
238 	{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
239 	{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
240 	{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
241 	{ .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, },
243 	{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
244 	{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
245 	{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
246 	{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
260 	{ .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T120C_MASK, },
261 	{ .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T140C_MASK, },