31 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest)			\  argument
33 		pci_read_config_word(dev, vsec + 0x6, dest);	\
34 		*dest >>= 4;					\
36 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \  argument
37 	pci_read_config_byte(dev, vsec + 0x8, dest)
39 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \  argument
40 	pci_read_config_byte(dev, vsec + 0x9, dest)
52 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \  argument
53 	pci_read_config_byte(dev, vsec + 0xa, dest)
62 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \  argument
63 	pci_read_config_word(dev, vsec + 0xc, dest)
64 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \  argument
65 	pci_read_config_byte(dev, vsec + 0xe, dest)
66 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \  argument
67 	pci_read_config_byte(dev, vsec + 0xf, dest)
68 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \  argument
69 	pci_read_config_word(dev, vsec + 0x10, dest)
71 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \  argument
72 	pci_read_config_byte(dev, vsec + 0x13, dest)
79 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \  argument
80 	pci_read_config_dword(dev, vsec + 0x20, dest)
81 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \  argument
82 	pci_read_config_dword(dev, vsec + 0x24, dest)
83 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \  argument
84 	pci_read_config_dword(dev, vsec + 0x28, dest)
85 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \  argument
86 	pci_read_config_dword(dev, vsec + 0x2c, dest)