230 	uint32_t clkrate, tmp;  in lpc32xx_nand_setup()  local
237 	clkrate = clk_get_rate(host->clk);  in lpc32xx_nand_setup()
238 	if (clkrate == 0)  in lpc32xx_nand_setup()
239 		clkrate = 104000000;  in lpc32xx_nand_setup()
255 	tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);  in lpc32xx_nand_setup()
256 	tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);  in lpc32xx_nand_setup()
257 	tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);  in lpc32xx_nand_setup()
258 	tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);  in lpc32xx_nand_setup()
259 	tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);  in lpc32xx_nand_setup()
260 	tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);  in lpc32xx_nand_setup()
261 	tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);  in lpc32xx_nand_setup()