Lines Matching refs:bp
45 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) argument
86 bp->dev ? (bp->dev->name) : "?", \
91 if (unlikely(bp->msg_enable & (__mask))) \
97 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \
103 if (unlikely(bp->msg_enable & (__mask))) \
110 if (unlikely(netif_msg_probe(bp))) \
113 bp->dev ? (bp->dev->name) : "?", \
122 bp->dev ? (bp->dev->name) : "?", \
132 if (unlikely(netif_msg_probe(bp))) \
133 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
137 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
141 bp->panic = 1; \
143 bnx2x_panic_dump(bp, true); \
148 bp->panic = 1; \
150 bnx2x_panic_dump(bp, false); \
161 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) argument
163 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) argument
164 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) argument
165 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) argument
167 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) argument
168 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) argument
169 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) argument
171 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) argument
172 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) argument
174 #define REG_RD_DMAE(bp, offset, valp, len32) \ argument
176 bnx2x_read_dmae(bp, offset, len32);\
177 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
180 #define REG_WR_DMAE(bp, offset, valp, len32) \ argument
182 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
183 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
187 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ argument
188 REG_WR_DMAE(bp, offset, valp, len32)
190 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ argument
192 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
193 bnx2x_write_big_buf_wb(bp, addr, len32); \
196 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ argument
198 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) argument
199 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) argument
201 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ argument
203 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) argument
204 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) argument
205 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ argument
207 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ argument
210 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) argument
211 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ argument
212 MF_CFG_ADDR(bp, field), (val))
213 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) argument
215 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ argument
216 (SHMEM2_RD((bp), size) > \
219 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) argument
220 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) argument
242 (&bp->def_status_blk->sp_sb.\
246 (&bp->def_status_blk->sp_sb.\
273 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ argument
274 (bp)->max_cos)
278 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ argument
281 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ argument
284 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) argument
286 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ argument
287 (UIO_DPM_ALIGN(bp) == UIO_DPM))
289 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ argument
290 (UIO_DPM_CID0_OFFSET(bp)))
292 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ argument
293 BNX2X_1st_NON_L2_ETH_CID(bp))
295 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) argument
297 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) argument
299 #define CNIC_SUPPORT(bp) ((bp)->cnic_support) argument
300 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) argument
301 #define CNIC_LOADED(bp) ((bp)->cnic_loaded) argument
302 #define FCOE_INIT(bp) ((bp)->fcoe_init) argument
315 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) argument
316 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ argument
317 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
320 #define FP_COS_TO_TXQ(fp, cos, bp) \ argument
321 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
334 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) argument
335 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) argument
368 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) argument
369 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ argument
372 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) argument
415 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
416 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
419 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ argument
421 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) argument
529 struct bnx2x *bp; /* parent */ member
604 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) argument
605 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) argument
606 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) argument
607 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) argument
723 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ argument
725 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) argument
726 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) argument
727 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) argument
728 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) argument
729 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ argument
733 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
734 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
735 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
788 #define NUM_BD_REQ BRB_SIZE(bp)
791 #define BD_TH_LO(bp) (NUM_BD_REQ + \ argument
793 FW_DROP_LEVEL(bp))
794 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) argument
796 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
798 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
836 #define NUM_RCQ_REQ BRB_SIZE(bp)
839 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ argument
841 FW_DROP_LEVEL(bp))
842 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) argument
865 #define DOORBELL(bp, cid, val) \ argument
867 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
945 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) argument
947 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) argument
971 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) argument
972 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) argument
973 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) argument
974 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) argument
975 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) argument
976 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) argument
977 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) argument
978 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) argument
979 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) argument
980 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) argument
981 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) argument
982 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) argument
983 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) argument
984 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) argument
985 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) argument
986 #define CHIP_IS_57840(bp) \ argument
987 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
988 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
989 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
990 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ argument
991 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
992 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) argument
993 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ argument
994 CHIP_IS_57711E(bp))
995 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ argument
996 CHIP_IS_57811_MF(bp) || \
997 CHIP_IS_57811_VF(bp))
998 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ argument
999 CHIP_IS_57712_MF(bp) || \
1000 CHIP_IS_57712_VF(bp))
1001 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ argument
1002 CHIP_IS_57800_MF(bp) || \
1003 CHIP_IS_57800_VF(bp) || \
1004 CHIP_IS_57810(bp) || \
1005 CHIP_IS_57810_MF(bp) || \
1006 CHIP_IS_57810_VF(bp) || \
1007 CHIP_IS_57811xx(bp) || \
1008 CHIP_IS_57840(bp) || \
1009 CHIP_IS_57840_MF(bp) || \
1010 CHIP_IS_57840_VF(bp))
1011 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) argument
1012 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) argument
1013 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
1017 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) argument
1021 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) argument
1023 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ argument
1024 !(CHIP_REV_VAL(bp) & 0x00001000))
1026 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ argument
1027 (CHIP_REV_VAL(bp) & 0x00001000))
1029 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ argument
1030 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
1032 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) argument
1033 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) argument
1034 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ argument
1037 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ argument
1038 CHIP_REV_SIM(bp) :\
1039 CHIP_REV_VAL(bp))
1040 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ argument
1041 (CHIP_REV(bp) == CHIP_REV_Bx))
1042 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ argument
1043 (CHIP_REV(bp) == CHIP_REV_Ax))
1055 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) argument
1076 #define CHIP_INT_MODE_IS_NBC(bp) \ argument
1077 (!CHIP_IS_E1x(bp) && \
1078 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
1079 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) argument
1085 #define CHIP_MODE(bp) (bp->common.chip_port_mode) argument
1086 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) argument
1274 #define bnx2x_sp(bp, var) (&bp->slowpath->var) argument
1275 #define bnx2x_sp_mapping(bp, var) \ argument
1276 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1331 (&bp->def_status_blk->sp_sb.\
1437 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) argument
1438 #define BP_PORT(bp) (bp->pfid & 1) argument
1439 #define BP_FUNC(bp) (bp->pfid) argument
1440 #define BP_ABS_FUNC(bp) (bp->pf_num) argument
1441 #define BP_VN(bp) ((bp)->pfid >> 1) argument
1442 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) argument
1443 #define BP_L_ID(bp) (BP_VN(bp) << 2) argument
1444 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ argument
1445 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1446 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) argument
1472 #define IRO (bp->iro_arr)
1572 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) argument
1575 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) argument
1576 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) argument
1578 #define IS_VF(bp) false argument
1579 #define IS_PF(bp) true argument
1582 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) argument
1583 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) argument
1584 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) argument
1629 #define IS_MF(bp) (bp->mf_mode != 0) argument
1630 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) argument
1631 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) argument
1632 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) argument
1634 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \ argument
1635 bp->mf_sub_mode == SUB_MF_MODE_UFP)
1727 #define BP_ILT(bp) ((bp)->ilt) argument
1733 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) argument
1740 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ argument
1741 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1742 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ argument
1743 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1744 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ argument
1802 #define GUNZIP_BUF(bp) (bp->gunzip_buf) argument
1803 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) argument
1804 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) argument
1812 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) argument
1822 #define INIT_OPS(bp) (bp->init_ops) argument
1823 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) argument
1824 #define INIT_DATA(bp) (bp->init_data) argument
1825 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) argument
1826 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) argument
1827 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) argument
1828 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) argument
1829 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) argument
1830 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) argument
1831 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) argument
1832 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) argument
1839 #define IS_SRIOV(bp) ((bp)->vfdb) argument
1930 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) argument
1931 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) argument
1932 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ argument
1933 (bp)->num_cnic_queues)
1934 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) argument
1936 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) argument
1938 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) argument
1972 #define for_each_cnic_queue(bp, var) \ argument
1973 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1975 if (skip_queue(bp, var)) \
1979 #define for_each_eth_queue(bp, var) \ argument
1980 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1982 #define for_each_nondefault_eth_queue(bp, var) \ argument
1983 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1985 #define for_each_queue(bp, var) \ argument
1986 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1987 if (skip_queue(bp, var)) \
1992 #define for_each_valid_rx_queue(bp, var) \ argument
1994 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1995 BNX2X_NUM_ETH_QUEUES(bp)); \
1997 if (skip_rx_queue(bp, var)) \
2001 #define for_each_rx_queue_cnic(bp, var) \ argument
2002 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2004 if (skip_rx_queue(bp, var)) \
2008 #define for_each_rx_queue(bp, var) \ argument
2009 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2010 if (skip_rx_queue(bp, var)) \
2015 #define for_each_valid_tx_queue(bp, var) \ argument
2017 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
2018 BNX2X_NUM_ETH_QUEUES(bp)); \
2020 if (skip_tx_queue(bp, var)) \
2024 #define for_each_tx_queue_cnic(bp, var) \ argument
2025 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2027 if (skip_tx_queue(bp, var)) \
2031 #define for_each_tx_queue(bp, var) \ argument
2032 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2033 if (skip_tx_queue(bp, var)) \
2037 #define for_each_nondefault_queue(bp, var) \ argument
2038 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2039 if (skip_queue(bp, var)) \
2049 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) argument
2054 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) argument
2056 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) argument
2076 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
2093 int bnx2x_del_all_macs(struct bnx2x *bp,
2098 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2099 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2101 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2102 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2103 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2104 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2105 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2107 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2110 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2111 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2113 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2116 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2119 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2121 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2125 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2126 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2127 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2129 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2132 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2133 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2135 void bnx2x_update_coalesce(struct bnx2x *bp);
2136 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2138 bool bnx2x_port_after_undi(struct bnx2x *bp);
2140 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, in reg_poll() argument
2146 val = REG_RD(bp, reg); in reg_poll()
2157 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2161 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2166 dma_free_coherent(&bp->pdev->dev, size, x, y); \
2260 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) argument
2267 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ argument
2268 BP_VN(bp))
2269 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ argument
2280 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ argument
2281 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2295 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ argument
2296 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2338 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \ argument
2339 IS_MF_FCOE_AFEX(bp))
2344 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2453 (&bp->def_status_blk->sp_sb.\
2463 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ argument
2464 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2483 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
2500 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2501 void bnx2x_notify_link_changed(struct bnx2x *bp);
2503 #define BNX2X_MF_SD_PROTOCOL(bp) \ argument
2504 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2506 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ argument
2507 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2509 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ argument
2510 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2512 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) argument
2513 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) argument
2514 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)) argument
2516 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp)) argument
2523 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \ argument
2526 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \ argument
2527 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2529 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \ argument
2530 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2532 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \ argument
2533 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
2535 #define IS_MF_FCOE_AFEX(bp) \ argument
2536 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
2538 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \ argument
2539 (IS_MF_SD(bp) && \
2540 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2541 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2543 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \ argument
2544 (IS_MF_SI(bp) && \
2545 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \
2546 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
2548 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \ argument
2549 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \
2550 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
2572 void bnx2x_set_local_cmng(struct bnx2x *bp);
2574 void bnx2x_update_mng_version(struct bnx2x *bp);
2576 #define MCPR_SCRATCH_BASE(bp) \ argument
2577 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2581 void bnx2x_init_ptp(struct bnx2x *bp);
2582 int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2583 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);