Lines Matching refs:bp
20 #define BP_ILT(bp) NULL argument
24 #define BP_FUNC(bp) 0 argument
28 #define BP_PORT(bp) 0 argument
43 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
44 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
45 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp,
49 static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, in bnx2x_init_str_wr() argument
55 REG_WR(bp, addr + i*4, data[i]); in bnx2x_init_str_wr()
58 static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, in bnx2x_init_ind_wr() argument
64 bnx2x_reg_wr_ind(bp, addr + i*4, data[i]); in bnx2x_init_ind_wr()
67 static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len, in bnx2x_write_big_buf() argument
70 if (bp->dmae_ready) in bnx2x_write_big_buf()
71 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len); in bnx2x_write_big_buf()
74 else if (wb && CHIP_IS_E1(bp)) in bnx2x_write_big_buf()
75 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len); in bnx2x_write_big_buf()
79 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len); in bnx2x_write_big_buf()
82 static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, in bnx2x_init_fill() argument
89 memset(GUNZIP_BUF(bp), (u8)fill, buf_len); in bnx2x_init_fill()
94 bnx2x_write_big_buf(bp, addr + i*4, cur_len, wb); in bnx2x_init_fill()
98 static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len) in bnx2x_write_big_buf_wb() argument
100 if (bp->dmae_ready) in bnx2x_write_big_buf_wb()
101 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len); in bnx2x_write_big_buf_wb()
104 else if (CHIP_IS_E1(bp)) in bnx2x_write_big_buf_wb()
105 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len); in bnx2x_write_big_buf_wb()
109 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len); in bnx2x_write_big_buf_wb()
112 static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, in bnx2x_init_wr_64() argument
125 u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i; in bnx2x_init_wr_64()
133 bnx2x_write_big_buf_wb(bp, addr + i*4, cur_len); in bnx2x_init_wr_64()
151 static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, in bnx2x_sel_blob() argument
155 data = INIT_TSEM_INT_TABLE_DATA(bp); in bnx2x_sel_blob()
158 data = INIT_CSEM_INT_TABLE_DATA(bp); in bnx2x_sel_blob()
161 data = INIT_USEM_INT_TABLE_DATA(bp); in bnx2x_sel_blob()
164 data = INIT_XSEM_INT_TABLE_DATA(bp); in bnx2x_sel_blob()
167 data = INIT_TSEM_PRAM_DATA(bp); in bnx2x_sel_blob()
170 data = INIT_CSEM_PRAM_DATA(bp); in bnx2x_sel_blob()
173 data = INIT_USEM_PRAM_DATA(bp); in bnx2x_sel_blob()
176 data = INIT_XSEM_PRAM_DATA(bp); in bnx2x_sel_blob()
181 static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, in bnx2x_init_wr_wb() argument
184 if (bp->dmae_ready) in bnx2x_init_wr_wb()
185 VIRT_WR_DMAE_LEN(bp, data, addr, len, 0); in bnx2x_init_wr_wb()
188 else if (CHIP_IS_E1(bp)) in bnx2x_init_wr_wb()
189 bnx2x_init_ind_wr(bp, addr, data, len); in bnx2x_init_wr_wb()
193 bnx2x_init_str_wr(bp, addr, data, len); in bnx2x_init_wr_wb()
196 static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo, in bnx2x_wr_64() argument
203 REG_WR_DMAE_LEN(bp, reg, wb_write, 2); in bnx2x_wr_64()
205 static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, in bnx2x_init_wr_zp() argument
212 data = bnx2x_sel_blob(bp, addr, data) + blob_off*4; in bnx2x_init_wr_zp()
214 rc = bnx2x_gunzip(bp, data, len); in bnx2x_init_wr_zp()
219 len = GUNZIP_OUTLEN(bp); in bnx2x_init_wr_zp()
221 ((u32 *)GUNZIP_BUF(bp))[i] = (__force u32) in bnx2x_init_wr_zp()
222 cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]); in bnx2x_init_wr_zp()
224 bnx2x_write_big_buf_wb(bp, addr, len); in bnx2x_init_wr_zp()
227 static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage) in bnx2x_init_block() argument
230 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, in bnx2x_init_block()
233 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, in bnx2x_init_block()
243 data_base = INIT_DATA(bp); in bnx2x_init_block()
247 op = (const union init_op *)&(INIT_OPS(bp)[op_idx]); in bnx2x_init_block()
260 REG_RD(bp, addr); in bnx2x_init_block()
263 REG_WR(bp, addr, op->write.val); in bnx2x_init_block()
266 bnx2x_init_str_wr(bp, addr, data, len); in bnx2x_init_block()
269 bnx2x_init_wr_wb(bp, addr, data, len); in bnx2x_init_block()
272 bnx2x_init_fill(bp, addr, 0, op->zero.len, 0); in bnx2x_init_block()
275 bnx2x_init_fill(bp, addr, 0, op->zero.len, 1); in bnx2x_init_block()
278 bnx2x_init_wr_zp(bp, addr, len, in bnx2x_init_block()
282 bnx2x_init_wr_64(bp, addr, data, len); in bnx2x_init_block()
288 if ((INIT_MODE_FLAGS(bp) & in bnx2x_init_block()
297 if ((INIT_MODE_FLAGS(bp) & in bnx2x_init_block()
473 static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, in bnx2x_init_pxp_arb() argument
488 if (CHIP_REV_IS_FPGA(bp)) { in bnx2x_init_pxp_arb()
495 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); in bnx2x_init_pxp_arb()
496 REG_WR(bp, read_arb_addr[i].add, in bnx2x_init_pxp_arb()
498 REG_WR(bp, read_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
506 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
509 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
512 REG_WR(bp, write_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
516 val = REG_RD(bp, write_arb_addr[i].l); in bnx2x_init_pxp_arb()
517 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
520 val = REG_RD(bp, write_arb_addr[i].add); in bnx2x_init_pxp_arb()
521 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
524 val = REG_RD(bp, write_arb_addr[i].ubound); in bnx2x_init_pxp_arb()
525 REG_WR(bp, write_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
533 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); in bnx2x_init_pxp_arb()
538 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); in bnx2x_init_pxp_arb()
540 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); in bnx2x_init_pxp_arb()
541 REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); in bnx2x_init_pxp_arb()
542 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); in bnx2x_init_pxp_arb()
543 REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); in bnx2x_init_pxp_arb()
545 if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD)) in bnx2x_init_pxp_arb()
546 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); in bnx2x_init_pxp_arb()
548 if (CHIP_IS_E3(bp)) in bnx2x_init_pxp_arb()
549 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order)); in bnx2x_init_pxp_arb()
550 else if (CHIP_IS_E2(bp)) in bnx2x_init_pxp_arb()
551 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order)); in bnx2x_init_pxp_arb()
553 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); in bnx2x_init_pxp_arb()
555 if (!CHIP_IS_E1(bp)) { in bnx2x_init_pxp_arb()
562 if (!CHIP_IS_E1H(bp)) { in bnx2x_init_pxp_arb()
565 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val); in bnx2x_init_pxp_arb()
568 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); in bnx2x_init_pxp_arb()
571 REG_WR(bp, PXP2_REG_WR_HC_MPS, val); in bnx2x_init_pxp_arb()
572 REG_WR(bp, PXP2_REG_WR_USDM_MPS, val); in bnx2x_init_pxp_arb()
573 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val); in bnx2x_init_pxp_arb()
574 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val); in bnx2x_init_pxp_arb()
575 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val); in bnx2x_init_pxp_arb()
576 REG_WR(bp, PXP2_REG_WR_QM_MPS, val); in bnx2x_init_pxp_arb()
577 REG_WR(bp, PXP2_REG_WR_TM_MPS, val); in bnx2x_init_pxp_arb()
578 REG_WR(bp, PXP2_REG_WR_SRC_MPS, val); in bnx2x_init_pxp_arb()
579 REG_WR(bp, PXP2_REG_WR_DBG_MPS, val); in bnx2x_init_pxp_arb()
580 REG_WR(bp, PXP2_REG_WR_CDU_MPS, val); in bnx2x_init_pxp_arb()
585 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST); in bnx2x_init_pxp_arb()
588 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20); in bnx2x_init_pxp_arb()
616 static int bnx2x_ilt_line_mem_op(struct bnx2x *bp, in bnx2x_ilt_line_mem_op() argument
631 static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num, in bnx2x_ilt_client_mem_op() argument
635 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_client_mem_op()
645 rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i], in bnx2x_ilt_client_mem_op()
651 static int bnx2x_ilt_mem_op_cnic(struct bnx2x *bp, u8 memop) in bnx2x_ilt_mem_op_cnic() argument
655 if (CONFIGURE_NIC_MODE(bp)) in bnx2x_ilt_mem_op_cnic()
656 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop); in bnx2x_ilt_mem_op_cnic()
658 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop); in bnx2x_ilt_mem_op_cnic()
663 static int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop) in bnx2x_ilt_mem_op() argument
665 int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop); in bnx2x_ilt_mem_op()
667 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop); in bnx2x_ilt_mem_op()
668 if (!rc && CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp)) in bnx2x_ilt_mem_op()
669 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop); in bnx2x_ilt_mem_op()
674 static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx, in bnx2x_ilt_line_wr() argument
679 if (CHIP_IS_E1(bp)) in bnx2x_ilt_line_wr()
684 bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping)); in bnx2x_ilt_line_wr()
687 static void bnx2x_ilt_line_init_op(struct bnx2x *bp, in bnx2x_ilt_line_init_op() argument
698 bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping); in bnx2x_ilt_line_init_op()
702 bnx2x_ilt_line_wr(bp, abs_idx, null_mapping); in bnx2x_ilt_line_init_op()
707 static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp, in bnx2x_ilt_boundry_init_op() argument
718 if (CHIP_IS_E1(bp)) { in bnx2x_ilt_boundry_init_op()
733 REG_WR(bp, start_reg + BP_FUNC(bp)*4, in bnx2x_ilt_boundry_init_op()
755 REG_WR(bp, start_reg, (ilt_start + ilt_cli->start)); in bnx2x_ilt_boundry_init_op()
756 REG_WR(bp, end_reg, (ilt_start + ilt_cli->end)); in bnx2x_ilt_boundry_init_op()
760 static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp, in bnx2x_ilt_client_init_op_ilt() argument
771 bnx2x_ilt_line_init_op(bp, ilt, i, initop); in bnx2x_ilt_client_init_op_ilt()
774 bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop); in bnx2x_ilt_client_init_op_ilt()
777 static void bnx2x_ilt_client_init_op(struct bnx2x *bp, in bnx2x_ilt_client_init_op() argument
780 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_client_init_op()
782 bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop); in bnx2x_ilt_client_init_op()
785 static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp, in bnx2x_ilt_client_id_init_op() argument
788 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_client_id_init_op()
791 bnx2x_ilt_client_init_op(bp, ilt_cli, initop); in bnx2x_ilt_client_id_init_op()
794 static void bnx2x_ilt_init_op_cnic(struct bnx2x *bp, u8 initop) in bnx2x_ilt_init_op_cnic() argument
796 if (CONFIGURE_NIC_MODE(bp)) in bnx2x_ilt_init_op_cnic()
797 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop); in bnx2x_ilt_init_op_cnic()
798 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop); in bnx2x_ilt_init_op_cnic()
801 static void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop) in bnx2x_ilt_init_op() argument
803 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop); in bnx2x_ilt_init_op()
804 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop); in bnx2x_ilt_init_op()
805 if (CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp)) in bnx2x_ilt_init_op()
806 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop); in bnx2x_ilt_init_op()
809 static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num, in bnx2x_ilt_init_client_psz() argument
812 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_init_client_psz()
822 REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12)); in bnx2x_ilt_init_client_psz()
833 static void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop) in bnx2x_ilt_init_page_size() argument
835 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU, in bnx2x_ilt_init_page_size()
837 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM, in bnx2x_ilt_init_page_size()
839 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC, in bnx2x_ilt_init_page_size()
841 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM, in bnx2x_ilt_init_page_size()
853 static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count, in bnx2x_qm_init_cid_count() argument
856 int port = BP_PORT(bp); in bnx2x_qm_init_cid_count()
863 REG_WR(bp, QM_REG_CONNNUM_0 + port*4, in bnx2x_qm_init_cid_count()
872 static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count, in bnx2x_qm_set_ptr_table() argument
878 REG_WR(bp, base_reg + i*4, in bnx2x_qm_set_ptr_table()
880 bnx2x_init_wr_wb(bp, reg + i*8, wb_data, 2); in bnx2x_qm_set_ptr_table()
885 static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count, in bnx2x_qm_init_ptr_table() argument
895 bnx2x_qm_set_ptr_table(bp, qm_cid_count, in bnx2x_qm_init_ptr_table()
897 if (CHIP_IS_E1H(bp)) in bnx2x_qm_init_ptr_table()
898 bnx2x_qm_set_ptr_table(bp, qm_cid_count, in bnx2x_qm_init_ptr_table()
911 static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2, in bnx2x_src_init_t2() argument
915 int port = BP_PORT(bp); in bnx2x_src_init_t2()
923 REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count); in bnx2x_src_init_t2()
925 bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16, in bnx2x_src_init_t2()
928 bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16, in bnx2x_src_init_t2()