Lines Matching refs:bp
220 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) in bnx2x_bits_en() argument
222 u32 val = REG_RD(bp, reg); in bnx2x_bits_en()
225 REG_WR(bp, reg, val); in bnx2x_bits_en()
229 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) in bnx2x_bits_dis() argument
231 u32 val = REG_RD(bp, reg); in bnx2x_bits_dis()
234 REG_WR(bp, reg, val); in bnx2x_bits_dis()
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa() local
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
269 link_status = REG_RD(bp, params->shmem_base + in bnx2x_check_lfa()
298 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
307 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
316 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
339 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
349 eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_check_lfa()
368 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) in bnx2x_get_epio() argument
380 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); in bnx2x_get_epio()
381 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in bnx2x_get_epio()
383 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; in bnx2x_get_epio()
385 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) in bnx2x_set_epio() argument
397 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); in bnx2x_set_epio()
403 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in bnx2x_set_epio()
406 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); in bnx2x_set_epio()
407 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in bnx2x_set_epio()
410 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) in bnx2x_set_cfg_pin() argument
415 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); in bnx2x_set_cfg_pin()
419 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); in bnx2x_set_cfg_pin()
423 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) in bnx2x_get_cfg_pin() argument
428 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); in bnx2x_get_cfg_pin()
432 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_get_cfg_pin()
443 struct bnx2x *bp = params->bp; in bnx2x_ets_e2e3a0_disabled() local
454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
473 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in bnx2x_ets_e2e3a0_disabled()
474 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in bnx2x_ets_e2e3a0_disabled()
475 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in bnx2x_ets_e2e3a0_disabled()
477 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in bnx2x_ets_e2e3a0_disabled()
478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); in bnx2x_ets_e2e3a0_disabled()
479 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); in bnx2x_ets_e2e3a0_disabled()
481 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_e2e3a0_disabled()
485 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
486 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
488 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
489 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
491 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_e2e3a0_disabled()
534 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_set_credit_upper_bound_nig() local
539 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
541 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
553 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
555 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
572 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_nig_disabled() local
581 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); in bnx2x_ets_e3b0_nig_disabled()
582 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
584 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); in bnx2x_ets_e3b0_nig_disabled()
585 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); in bnx2x_ets_e3b0_nig_disabled()
590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : in bnx2x_ets_e3b0_nig_disabled()
597 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); in bnx2x_ets_e3b0_nig_disabled()
598 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
601 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, in bnx2x_ets_e3b0_nig_disabled()
603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); in bnx2x_ets_e3b0_nig_disabled()
614 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); in bnx2x_ets_e3b0_nig_disabled()
616 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); in bnx2x_ets_e3b0_nig_disabled()
618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_nig_disabled()
627 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : in bnx2x_ets_e3b0_nig_disabled()
629 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : in bnx2x_ets_e3b0_nig_disabled()
631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : in bnx2x_ets_e3b0_nig_disabled()
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : in bnx2x_ets_e3b0_nig_disabled()
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : in bnx2x_ets_e3b0_nig_disabled()
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : in bnx2x_ets_e3b0_nig_disabled()
640 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); in bnx2x_ets_e3b0_nig_disabled()
641 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); in bnx2x_ets_e3b0_nig_disabled()
642 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); in bnx2x_ets_e3b0_nig_disabled()
656 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_set_credit_upper_bound_pbf() local
675 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
688 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_pbf_disabled() local
701 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); in bnx2x_ets_e3b0_pbf_disabled()
704 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
709 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); in bnx2x_ets_e3b0_pbf_disabled()
712 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : in bnx2x_ets_e3b0_pbf_disabled()
718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_pbf_disabled()
721 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_pbf_disabled()
735 REG_WR(bp, base_weight + (0x4 * i), 0); in bnx2x_ets_e3b0_pbf_disabled()
747 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_disabled() local
749 if (!CHIP_IS_E3B0(bp)) { in bnx2x_ets_e3b0_disabled()
770 struct bnx2x *bp = params->bp; in bnx2x_ets_disabled() local
773 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) in bnx2x_ets_disabled()
775 else if (CHIP_IS_E3B0(bp)) in bnx2x_ets_disabled()
795 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_cli_map() local
802 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : in bnx2x_ets_e3b0_cli_map()
805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_cli_map()
808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_cli_map()
812 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_cli_map()
824 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, in bnx2x_ets_e3b0_set_cos_bw() argument
885 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); in bnx2x_ets_e3b0_set_cos_bw()
887 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); in bnx2x_ets_e3b0_set_cos_bw()
901 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_get_total_bw() local
961 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_sp_pri_to_cos_set() local
1042 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_sp_set_pri_cli_reg() local
1109 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1112 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1118 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1120 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1123 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1136 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_config() local
1149 if (!CHIP_IS_E3B0(bp)) { in bnx2x_ets_e3b0_config()
1187 bp, cos_entry, min_w_val_nig, min_w_val_pbf, in bnx2x_ets_e3b0_config()
1237 struct bnx2x *bp = params->bp; in bnx2x_ets_bw_limit_common() local
1243 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); in bnx2x_ets_bw_limit_common()
1250 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); in bnx2x_ets_bw_limit_common()
1252 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, in bnx2x_ets_bw_limit_common()
1254 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, in bnx2x_ets_bw_limit_common()
1258 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); in bnx2x_ets_bw_limit_common()
1261 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_bw_limit_common()
1269 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_bw_limit_common()
1272 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1274 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1282 struct bnx2x *bp = params->bp; in bnx2x_ets_bw_limit() local
1303 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); in bnx2x_ets_bw_limit()
1304 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); in bnx2x_ets_bw_limit()
1306 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); in bnx2x_ets_bw_limit()
1307 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); in bnx2x_ets_bw_limit()
1313 struct bnx2x *bp = params->bp; in bnx2x_ets_strict() local
1324 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); in bnx2x_ets_strict()
1328 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1330 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_strict()
1332 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1335 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); in bnx2x_ets_strict()
1345 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); in bnx2x_ets_strict()
1357 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_xmac() local
1388 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1389 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1390 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1396 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1397 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1398 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1402 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, in bnx2x_update_pfc_xmac()
1407 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, in bnx2x_update_pfc_xmac()
1417 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, in bnx2x_set_mdio_clk() argument
1425 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_set_mdio_clk()
1427 if (USES_WARPCORE(bp)) in bnx2x_set_mdio_clk()
1443 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); in bnx2x_set_mdio_clk()
1447 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, in bnx2x_set_mdio_emac_per_phy() argument
1454 bnx2x_set_mdio_clk(bp, params->chip_id, in bnx2x_set_mdio_emac_per_phy()
1458 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) in bnx2x_is_4_port_mode() argument
1462 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); in bnx2x_is_4_port_mode()
1468 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); in bnx2x_is_4_port_mode()
1475 struct bnx2x *bp = params->bp; in bnx2x_emac_init() local
1481 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_init()
1484 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_emac_init()
1489 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_init()
1490 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); in bnx2x_emac_init()
1494 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_init()
1503 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_emac_init()
1507 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); in bnx2x_emac_init()
1513 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); in bnx2x_emac_init()
1520 struct bnx2x *bp = params->bp; in bnx2x_set_xumac_nig() local
1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in bnx2x_set_xumac_nig()
1524 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in bnx2x_set_xumac_nig()
1526 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in bnx2x_set_xumac_nig()
1534 struct bnx2x *bp = params->bp; in bnx2x_set_umac_rxtx() local
1535 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_umac_rxtx()
1538 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); in bnx2x_set_umac_rxtx()
1546 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_set_umac_rxtx()
1554 struct bnx2x *bp = params->bp; in bnx2x_umac_enable() local
1556 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_umac_enable()
1560 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_umac_enable()
1566 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_umac_enable()
1599 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1605 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, in bnx2x_umac_enable()
1607 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in bnx2x_umac_enable()
1609 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in bnx2x_umac_enable()
1613 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, in bnx2x_umac_enable()
1618 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, in bnx2x_umac_enable()
1626 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1635 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1640 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_umac_enable()
1650 struct bnx2x *bp = params->bp; in bnx2x_xmac_init() local
1651 u32 is_port4mode = bnx2x_is_4_port_mode(bp); in bnx2x_xmac_init()
1659 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || in bnx2x_xmac_init()
1660 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || in bnx2x_xmac_init()
1661 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && in bnx2x_xmac_init()
1663 (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_xmac_init()
1671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1675 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1681 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); in bnx2x_xmac_init()
1684 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1687 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); in bnx2x_xmac_init()
1692 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1697 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); in bnx2x_xmac_init()
1701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1713 struct bnx2x *bp = params->bp; in bnx2x_set_xmac_rxtx() local
1717 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_xmac_rxtx()
1723 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); in bnx2x_set_xmac_rxtx()
1724 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1726 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1729 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); in bnx2x_set_xmac_rxtx()
1734 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_set_xmac_rxtx()
1742 struct bnx2x *bp = params->bp; in bnx2x_xmac_enable() local
1756 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in bnx2x_xmac_enable()
1762 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, in bnx2x_xmac_enable()
1765 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_xmac_enable()
1766 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_xmac_enable()
1771 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); in bnx2x_xmac_enable()
1774 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); in bnx2x_xmac_enable()
1781 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); in bnx2x_xmac_enable()
1782 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); in bnx2x_xmac_enable()
1784 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); in bnx2x_xmac_enable()
1799 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_xmac_enable()
1811 struct bnx2x *bp = params->bp; in bnx2x_emac_enable() local
1819 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_enable()
1823 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); in bnx2x_emac_enable()
1833 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); in bnx2x_emac_enable()
1835 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_emac_enable()
1840 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in bnx2x_emac_enable()
1843 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, in bnx2x_emac_enable()
1845 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1849 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, in bnx2x_emac_enable()
1852 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1858 bnx2x_bits_en(bp, emac_base + in bnx2x_emac_enable()
1863 bnx2x_bits_en(bp, emac_base + in bnx2x_emac_enable()
1868 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1872 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); in bnx2x_emac_enable()
1882 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); in bnx2x_emac_enable()
1886 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, in bnx2x_emac_enable()
1891 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, in bnx2x_emac_enable()
1898 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); in bnx2x_emac_enable()
1901 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_enable()
1906 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); in bnx2x_emac_enable()
1909 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); in bnx2x_emac_enable()
1912 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, in bnx2x_emac_enable()
1917 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); in bnx2x_emac_enable()
1920 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); in bnx2x_emac_enable()
1921 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1922 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1925 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); in bnx2x_emac_enable()
1932 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_emac_enable()
1933 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); in bnx2x_emac_enable()
1935 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1945 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_bmac1() local
1957 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac1()
1967 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac1()
1978 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_bmac2() local
1990 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2001 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2013 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, in bnx2x_update_pfc_bmac2()
2024 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2037 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, in bnx2x_update_pfc_bmac2()
2052 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2060 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, in bnx2x_pfc_nig_rx_priority_mask() argument
2099 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); in bnx2x_pfc_nig_rx_priority_mask()
2105 struct bnx2x *bp = params->bp; in bnx2x_update_mng() local
2107 REG_WR(bp, params->shmem_base + in bnx2x_update_mng()
2114 struct bnx2x *bp = params->bp; in bnx2x_update_link_attr() local
2116 if (SHMEM2_HAS(bp, link_attr_sync)) in bnx2x_update_link_attr()
2117 REG_WR(bp, params->shmem2_base + in bnx2x_update_link_attr()
2129 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_nig() local
2140 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2149 if (CHIP_IS_E3(bp)) in bnx2x_update_pfc_nig()
2170 if (CHIP_IS_E3(bp)) in bnx2x_update_pfc_nig()
2171 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : in bnx2x_update_pfc_nig()
2173 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : in bnx2x_update_pfc_nig()
2175 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : in bnx2x_update_pfc_nig()
2177 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : in bnx2x_update_pfc_nig()
2180 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : in bnx2x_update_pfc_nig()
2183 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2186 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : in bnx2x_update_pfc_nig()
2190 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : in bnx2x_update_pfc_nig()
2194 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : in bnx2x_update_pfc_nig()
2202 bnx2x_pfc_nig_rx_priority_mask(bp, i, in bnx2x_update_pfc_nig()
2205 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2209 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2213 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : in bnx2x_update_pfc_nig()
2227 struct bnx2x *bp = params->bp; in bnx2x_update_pfc() local
2245 if (CHIP_IS_E3(bp)) { in bnx2x_update_pfc()
2249 val = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_update_pfc()
2257 if (CHIP_IS_E2(bp)) in bnx2x_update_pfc()
2267 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in bnx2x_update_pfc()
2276 struct bnx2x *bp = params->bp; in bnx2x_bmac1_enable() local
2288 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, in bnx2x_bmac1_enable()
2298 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); in bnx2x_bmac1_enable()
2308 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_bmac1_enable()
2313 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2320 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2325 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2330 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, in bnx2x_bmac1_enable()
2340 struct bnx2x *bp = params->bp; in bnx2x_bmac2_enable() local
2350 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_bmac2_enable()
2356 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, in bnx2x_bmac2_enable()
2368 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, in bnx2x_bmac2_enable()
2376 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, in bnx2x_bmac2_enable()
2383 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2389 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2394 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2407 struct bnx2x *bp = params->bp; in bnx2x_bmac_enable() local
2411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_bmac_enable()
2416 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_bmac_enable()
2420 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2423 if (CHIP_IS_E2(bp)) in bnx2x_bmac_enable()
2427 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); in bnx2x_bmac_enable()
2428 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); in bnx2x_bmac_enable()
2429 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); in bnx2x_bmac_enable()
2435 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_bmac_enable()
2436 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2437 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); in bnx2x_bmac_enable()
2438 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2439 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); in bnx2x_bmac_enable()
2440 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2446 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) in bnx2x_set_bmac_rx() argument
2451 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); in bnx2x_set_bmac_rx()
2453 if (CHIP_IS_E2(bp)) in bnx2x_set_bmac_rx()
2458 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_bmac_rx()
2462 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); in bnx2x_set_bmac_rx()
2467 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); in bnx2x_set_bmac_rx()
2475 struct bnx2x *bp = params->bp; in bnx2x_pbf_update() local
2481 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); in bnx2x_pbf_update()
2484 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); in bnx2x_pbf_update()
2485 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2490 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2493 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2505 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); in bnx2x_pbf_update()
2507 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); in bnx2x_pbf_update()
2514 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_pbf_update()
2516 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); in bnx2x_pbf_update()
2528 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); in bnx2x_pbf_update()
2533 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); in bnx2x_pbf_update()
2535 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); in bnx2x_pbf_update()
2538 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); in bnx2x_pbf_update()
2557 static u32 bnx2x_get_emac_base(struct bnx2x *bp, in bnx2x_get_emac_base() argument
2565 if (REG_RD(bp, NIG_REG_PORT_SWAP)) in bnx2x_get_emac_base()
2571 if (REG_RD(bp, NIG_REG_PORT_SWAP)) in bnx2x_get_emac_base()
2592 static int bnx2x_cl22_write(struct bnx2x *bp, in bnx2x_cl22_write() argument
2600 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_write()
2601 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2608 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2613 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_write()
2623 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2627 static int bnx2x_cl22_read(struct bnx2x *bp, in bnx2x_cl22_read() argument
2636 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_read()
2637 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2644 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2649 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_read()
2662 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2669 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read() argument
2677 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_cl45_read()
2678 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_cl45_read()
2679 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_read()
2683 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2689 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2694 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_read()
2702 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_read()
2710 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2715 val = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_read()
2724 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_read()
2734 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_read()
2739 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2744 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_write() argument
2752 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_cl45_write()
2753 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_cl45_write()
2754 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_write()
2758 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2765 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2770 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_write()
2778 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_write()
2785 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2790 tmp = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_write()
2799 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_write()
2808 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_write()
2812 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2822 struct bnx2x *bp = params->bp; in bnx2x_eee_has_cap() local
2824 if (REG_RD(bp, params->shmem2_base) <= in bnx2x_eee_has_cap()
2874 struct bnx2x *bp = params->bp; in bnx2x_eee_calc_timer() local
2889 eee_mode = ((REG_RD(bp, params->shmem_base + in bnx2x_eee_calc_timer()
2907 struct bnx2x *bp = params->bp; in bnx2x_eee_set_timers() local
2912 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in bnx2x_eee_set_timers()
2959 struct bnx2x *bp = params->bp; in bnx2x_eee_disable() local
2962 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in bnx2x_eee_disable()
2964 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); in bnx2x_eee_disable()
2975 struct bnx2x *bp = params->bp; in bnx2x_eee_advertise() local
2979 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in bnx2x_eee_advertise()
2990 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); in bnx2x_eee_advertise()
3000 struct bnx2x *bp = params->bp; in bnx2x_update_mng_eee() local
3003 REG_WR(bp, params->shmem2_base + in bnx2x_update_mng_eee()
3012 struct bnx2x *bp = params->bp; in bnx2x_eee_an_resolve() local
3017 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); in bnx2x_eee_an_resolve()
3018 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); in bnx2x_eee_an_resolve()
3063 struct bnx2x *bp = params->bp; in bnx2x_bsc_module_sel() local
3066 board_cfg = REG_RD(bp, params->shmem_base + in bnx2x_bsc_module_sel()
3074 sfp_ctrl = REG_RD(bp, params->shmem_base + in bnx2x_bsc_module_sel()
3081 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); in bnx2x_bsc_module_sel()
3085 struct bnx2x *bp, in bnx2x_bsc_read() argument
3105 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3107 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3111 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); in bnx2x_bsc_read()
3118 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3122 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3125 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3142 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3146 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3149 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3160 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); in bnx2x_bsc_read()
3171 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read_or_write() argument
3175 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_or_write()
3176 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); in bnx2x_cl45_read_or_write()
3179 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, in bnx2x_cl45_read_and_write() argument
3184 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_and_write()
3185 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); in bnx2x_cl45_read_and_write()
3197 return bnx2x_cl45_read(params->bp, in bnx2x_phy_read()
3214 return bnx2x_cl45_write(params->bp, in bnx2x_phy_write()
3225 struct bnx2x *bp = params->bp; in bnx2x_get_warpcore_lane() local
3229 path = BP_PATH(bp); in bnx2x_get_warpcore_lane()
3232 if (bnx2x_is_4_port_mode(bp)) { in bnx2x_get_warpcore_lane()
3236 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3240 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); in bnx2x_get_warpcore_lane()
3246 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3250 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); in bnx2x_get_warpcore_lane()
3260 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3265 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); in bnx2x_get_warpcore_lane()
3280 struct bnx2x *bp = params->bp; in bnx2x_set_aer_mmd() local
3288 if (USES_WARPCORE(bp)) { in bnx2x_set_aer_mmd()
3298 } else if (CHIP_IS_E2(bp)) in bnx2x_set_aer_mmd()
3303 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_aer_mmd()
3312 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) in bnx2x_set_serdes_access() argument
3317 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); in bnx2x_set_serdes_access()
3318 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); in bnx2x_set_serdes_access()
3320 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); in bnx2x_set_serdes_access()
3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); in bnx2x_set_serdes_access()
3326 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) in bnx2x_serdes_deassert() argument
3335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_serdes_deassert()
3337 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_serdes_deassert()
3339 bnx2x_set_serdes_access(bp, port); in bnx2x_serdes_deassert()
3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, in bnx2x_serdes_deassert()
3349 struct bnx2x *bp = params->bp; in bnx2x_xgxs_specific_func() local
3353 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in bnx2x_xgxs_specific_func()
3354 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in bnx2x_xgxs_specific_func()
3362 struct bnx2x *bp = params->bp; in bnx2x_xgxs_deassert() local
3371 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_xgxs_deassert()
3373 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_xgxs_deassert()
3381 struct bnx2x *bp = params->bp; in bnx2x_calc_ieee_aneg_adv() local
3422 struct bnx2x *bp = params->bp; in set_phy_vars() local
3465 struct bnx2x *bp = params->bp; in bnx2x_ext_phy_set_pause() local
3467 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); in bnx2x_ext_phy_set_pause()
3484 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); in bnx2x_ext_phy_set_pause()
3522 struct bnx2x *bp = params->bp; in bnx2x_ext_phy_update_adv_fc() local
3524 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); in bnx2x_ext_phy_update_adv_fc()
3525 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); in bnx2x_ext_phy_update_adv_fc()
3526 } else if (CHIP_IS_E3(bp) && in bnx2x_ext_phy_update_adv_fc()
3530 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3537 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3539 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3542 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3544 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3554 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3557 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3612 struct bnx2x *bp = params->bp; in bnx2x_warpcore_enable_AN_KR2() local
3635 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR2()
3639 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR2()
3651 struct bnx2x *bp = params->bp; in bnx2x_disable_kr2() local
3674 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_disable_kr2()
3685 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_lpi_passthrough() local
3688 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3690 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3698 struct bnx2x *bp = params->bp; in bnx2x_warpcore_restart_AN_KR() local
3700 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_restart_AN_KR()
3702 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_restart_AN_KR()
3714 struct bnx2x *bp = params->bp; in bnx2x_warpcore_enable_AN_KR() local
3728 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR()
3731 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3735 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3746 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); in bnx2x_warpcore_enable_AN_KR()
3755 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3758 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3766 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3771 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3774 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3777 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3782 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3786 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3792 if (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_enable_AN_KR()
3796 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3805 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3809 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3816 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3819 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3823 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3830 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3832 wc_lane_config = REG_RD(bp, params->shmem_base + in bnx2x_warpcore_enable_AN_KR()
3835 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3865 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_10G_KR() local
3881 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_set_10G_KR()
3886 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_10G_KR()
3889 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3892 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3895 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3898 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3903 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3906 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3910 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3914 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3918 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3922 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3924 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3933 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_10G_XFI() local
3938 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3942 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3946 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in bnx2x_warpcore_set_10G_XFI()
3949 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3953 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3957 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3961 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3966 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3968 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3973 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3983 cfg_tap_val = REG_RD(bp, params->shmem_base + in bnx2x_warpcore_set_10G_XFI()
4008 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4013 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4016 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4021 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4025 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4031 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4035 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4039 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4047 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_20G_force_KR2() local
4049 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4053 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4058 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4060 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4063 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4067 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4071 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4074 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4077 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4081 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4083 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4087 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4090 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4096 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, in bnx2x_warpcore_set_20G_DXGXS() argument
4101 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4105 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4108 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4111 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4114 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4117 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4120 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4123 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4126 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4129 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4133 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4137 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4141 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4145 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4155 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_sgmii_speed() local
4159 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4166 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4171 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4192 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4197 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4203 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4210 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4215 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4217 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4222 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4227 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4232 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, in bnx2x_warpcore_reset_lane() argument
4238 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4244 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4246 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4254 struct bnx2x *bp = params->bp; in bnx2x_warpcore_clear_regs() local
4273 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4277 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, in bnx2x_warpcore_clear_regs()
4281 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4286 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, in bnx2x_get_mod_abs_int_cfg() argument
4294 if (CHIP_IS_E3(bp)) { in bnx2x_get_mod_abs_int_cfg()
4295 cfg_pin = (REG_RD(bp, shmem_base + in bnx2x_get_mod_abs_int_cfg()
4328 struct bnx2x *bp = params->bp; in bnx2x_is_sfp_module_plugged() local
4331 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, in bnx2x_is_sfp_module_plugged()
4335 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_is_sfp_module_plugged()
4347 struct bnx2x *bp = params->bp; in bnx2x_warpcore_get_sigdet() local
4351 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, in bnx2x_warpcore_get_sigdet()
4361 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_runtime() local
4372 serdes_net_if = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_config_runtime()
4380 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, in bnx2x_warpcore_config_runtime()
4390 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_runtime()
4391 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_runtime()
4394 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_config_runtime()
4414 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_sfi() local
4431 struct bnx2x *bp = params->bp; in bnx2x_sfp_e3_set_transmitter() local
4435 cfg_pin = REG_RD(bp, params->shmem_base + in bnx2x_sfp_e3_set_transmitter()
4443 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); in bnx2x_sfp_e3_set_transmitter()
4445 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); in bnx2x_sfp_e3_set_transmitter()
4452 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_init() local
4456 serdes_net_if = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_config_init()
4464 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_init()
4530 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); in bnx2x_warpcore_config_init()
4552 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_init()
4559 struct bnx2x *bp = params->bp; in bnx2x_warpcore_link_reset() local
4562 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_warpcore_link_reset()
4565 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_link_reset()
4569 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4572 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4576 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_link_reset()
4579 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4583 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4587 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4592 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4595 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4604 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4614 struct bnx2x *bp = params->bp; in bnx2x_set_warpcore_loopback() local
4625 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_warpcore_loopback()
4628 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4633 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4638 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4646 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4649 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4659 struct bnx2x *bp = params->bp; in bnx2x_sync_link() local
4727 USES_WARPCORE(bp) && in bnx2x_sync_link()
4734 if (USES_WARPCORE(bp)) in bnx2x_sync_link()
4739 if (USES_WARPCORE(bp)) in bnx2x_sync_link()
4765 struct bnx2x *bp = params->bp; in bnx2x_link_status_update() local
4771 vars->link_status = REG_RD(bp, params->shmem_base + in bnx2x_link_status_update()
4781 vars->eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_link_status_update()
4791 media_types = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4809 vars->aeu_int_mask = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4819 if (SHMEM2_HAS(bp, link_attr_sync)) in bnx2x_link_status_update()
4820 params->link_attr_sync = SHMEM2_RD(bp, in bnx2x_link_status_update()
4832 struct bnx2x *bp = params->bp; in bnx2x_set_master_ln() local
4839 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4844 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4854 struct bnx2x *bp = params->bp; in bnx2x_reset_unicore() local
4857 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4862 CL22_WR_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4868 bnx2x_set_serdes_access(bp, params->port); in bnx2x_reset_unicore()
4875 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4886 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_reset_unicore()
4897 struct bnx2x *bp = params->bp; in bnx2x_set_swap_lanes() local
4911 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4918 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4924 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4930 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4939 struct bnx2x *bp = params->bp; in bnx2x_set_parallel_detection() local
4941 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4951 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4961 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4966 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4975 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4981 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4994 struct bnx2x *bp = params->bp; in bnx2x_set_autoneg() local
4998 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5009 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5015 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5026 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5031 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5044 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5051 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5057 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5065 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5076 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5087 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5097 struct bnx2x *bp = params->bp; in bnx2x_program_serdes() local
5101 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5109 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5116 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5136 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5145 struct bnx2x *bp = params->bp; in bnx2x_set_brcm_cl37_advertisement() local
5153 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5157 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5166 struct bnx2x *bp = params->bp; in bnx2x_set_ieee_aneg_advertisement() local
5170 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5173 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5178 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5187 struct bnx2x *bp = params->bp; in bnx2x_restart_autoneg() local
5194 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5199 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5207 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5214 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5227 struct bnx2x *bp = params->bp; in bnx2x_initialize_sgmii_process() local
5232 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5241 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5251 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5282 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5298 struct bnx2x *bp = params->bp; in bnx2x_direct_parallel_detect_used() local
5302 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5306 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5316 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5337 struct bnx2x *bp = params->bp; in bnx2x_update_adv_fc() local
5344 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5348 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5358 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5362 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5381 struct bnx2x *bp = params->bp; in bnx2x_flow_ctrl_resolve() local
5407 struct bnx2x *bp = params->bp; in bnx2x_check_fallback_to_cl37() local
5411 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5419 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5426 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5442 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5463 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5492 struct bnx2x *bp = params->bp; in bnx2x_get_link_speed_duplex() local
5580 struct bnx2x *bp = params->bp; in bnx2x_link_settings_status() local
5586 CL22_RD_OVER_CL45(bp, phy, in bnx2x_link_settings_status()
5623 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, in bnx2x_link_settings_status()
5634 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, in bnx2x_link_settings_status()
5654 struct bnx2x *bp = params->bp; in bnx2x_warpcore_read_status() local
5662 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5664 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5670 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5672 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5680 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5691 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5693 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5701 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5709 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5725 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5736 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5750 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5753 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5777 struct bnx2x *bp = params->bp; in bnx2x_set_gmii_tx_driver() local
5784 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5798 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5807 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5817 struct bnx2x *bp = params->bp; in bnx2x_emac_program() local
5822 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + in bnx2x_emac_program()
5853 bnx2x_bits_en(bp, in bnx2x_emac_program()
5866 struct bnx2x *bp = params->bp; in bnx2x_set_preemphasis() local
5870 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5878 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5889 struct bnx2x *bp = params->bp; in bnx2x_xgxs_config_init() local
5973 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, in bnx2x_wait_reset_complete() argument
5981 bnx2x_cl22_read(bp, phy, in bnx2x_wait_reset_complete()
5984 bnx2x_cl45_read(bp, phy, in bnx2x_wait_reset_complete()
5993 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_wait_reset_complete()
6004 struct bnx2x *bp = params->bp; in bnx2x_link_int_enable() local
6007 if (CHIP_IS_E3(bp)) { in bnx2x_link_int_enable()
6032 bnx2x_bits_en(bp, in bnx2x_link_int_enable()
6038 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); in bnx2x_link_int_enable()
6040 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), in bnx2x_link_int_enable()
6041 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), in bnx2x_link_int_enable()
6042 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); in bnx2x_link_int_enable()
6044 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_int_enable()
6045 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_int_enable()
6048 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, in bnx2x_rearm_latch_signal() argument
6058 latch_status = REG_RD(bp, in bnx2x_rearm_latch_signal()
6063 bnx2x_bits_en(bp, in bnx2x_rearm_latch_signal()
6068 bnx2x_bits_dis(bp, in bnx2x_rearm_latch_signal()
6076 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, in bnx2x_rearm_latch_signal()
6085 struct bnx2x *bp = params->bp; in bnx2x_link_int_ack() local
6091 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, in bnx2x_link_int_ack()
6096 if (USES_WARPCORE(bp)) in bnx2x_link_int_ack()
6116 bnx2x_bits_en(bp, in bnx2x_link_int_ack()
6171 struct bnx2x *bp; in bnx2x_get_ext_phy_fw_version() local
6178 bp = params->bp; in bnx2x_get_ext_phy_fw_version()
6182 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); in bnx2x_get_ext_phy_fw_version()
6192 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); in bnx2x_get_ext_phy_fw_version()
6212 struct bnx2x *bp = params->bp; in bnx2x_set_xgxs_loopback() local
6219 if (!CHIP_IS_E3(bp)) { in bnx2x_set_xgxs_loopback()
6221 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + in bnx2x_set_xgxs_loopback()
6224 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6228 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6234 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6243 if (!CHIP_IS_E3(bp)) { in bnx2x_set_xgxs_loopback()
6245 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6251 bnx2x_cl45_read(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6255 bnx2x_cl45_write(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6272 struct bnx2x *bp = params->bp; in bnx2x_set_led() local
6287 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); in bnx2x_set_led()
6288 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6291 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6300 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); in bnx2x_set_led()
6314 CHIP_IS_E2(bp) && params->num_phys == 2) { in bnx2x_set_led()
6318 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6319 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6321 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6322 EMAC_WR(bp, EMAC_REG_EMAC_LED, in bnx2x_set_led()
6336 if ((!CHIP_IS_E3(bp)) || in bnx2x_set_led()
6337 (CHIP_IS_E3(bp) && in bnx2x_set_led()
6339 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6341 if (CHIP_IS_E1x(bp) || in bnx2x_set_led()
6342 CHIP_IS_E2(bp) || in bnx2x_set_led()
6344 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6346 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6351 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6352 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6353 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | in bnx2x_set_led()
6365 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6369 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); in bnx2x_set_led()
6371 if (CHIP_IS_E3(bp)) in bnx2x_set_led()
6372 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6375 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6377 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + in bnx2x_set_led()
6379 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6380 EMAC_WR(bp, EMAC_REG_EMAC_LED, in bnx2x_set_led()
6383 if (CHIP_IS_E1(bp) && in bnx2x_set_led()
6389 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 in bnx2x_set_led()
6391 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + in bnx2x_set_led()
6393 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + in bnx2x_set_led()
6414 struct bnx2x *bp = params->bp; in bnx2x_test_link() local
6420 if (CHIP_IS_E3(bp)) { in bnx2x_test_link()
6425 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6427 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6433 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6443 CL22_RD_OVER_CL45(bp, int_phy, in bnx2x_test_link()
6496 struct bnx2x *bp = params->bp; in bnx2x_link_initialize() local
6508 if (!USES_WARPCORE(bp)) in bnx2x_link_initialize()
6519 (CHIP_IS_E1x(bp) || in bnx2x_link_initialize()
6520 CHIP_IS_E2(bp))) in bnx2x_link_initialize()
6561 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + in bnx2x_link_initialize()
6574 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in bnx2x_int_link_reset()
6581 struct bnx2x *bp = params->bp; in bnx2x_common_ext_link_reset() local
6584 if (CHIP_IS_E2(bp)) in bnx2x_common_ext_link_reset()
6585 gpio_port = BP_PATH(bp); in bnx2x_common_ext_link_reset()
6588 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_common_ext_link_reset()
6591 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_common_ext_link_reset()
6600 struct bnx2x *bp = params->bp; in bnx2x_update_link_down() local
6615 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_update_link_down()
6618 if (!CHIP_IS_E3(bp)) in bnx2x_update_link_down()
6619 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_update_link_down()
6623 if (CHIP_IS_E1x(bp) || in bnx2x_update_link_down()
6624 CHIP_IS_E2(bp)) in bnx2x_update_link_down()
6625 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_update_link_down()
6627 if (CHIP_IS_E3(bp)) { in bnx2x_update_link_down()
6629 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in bnx2x_update_link_down()
6631 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in bnx2x_update_link_down()
6648 struct bnx2x *bp = params->bp; in bnx2x_update_link_up() local
6663 if (USES_WARPCORE(bp)) { in bnx2x_update_link_up()
6680 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + in bnx2x_update_link_up()
6682 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); in bnx2x_update_link_up()
6683 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + in bnx2x_update_link_up()
6687 if ((CHIP_IS_E1x(bp) || in bnx2x_update_link_up()
6688 CHIP_IS_E2(bp))) { in bnx2x_update_link_up()
6714 if (CHIP_IS_E1x(bp)) in bnx2x_update_link_up()
6719 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); in bnx2x_update_link_up()
6748 struct bnx2x *bp = params->bp; in bnx2x_link_update() local
6772 if (USES_WARPCORE(bp)) in bnx2x_link_update()
6777 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); in bnx2x_link_update()
6779 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + in bnx2x_link_update()
6782 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), in bnx2x_link_update()
6784 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); in bnx2x_link_update()
6787 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_update()
6788 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_update()
6791 if (!CHIP_IS_E3(bp)) in bnx2x_link_update()
6792 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_update()
6910 bnx2x_rearm_latch_signal(bp, port, in bnx2x_link_update()
6933 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in bnx2x_link_update()
6993 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); in bnx2x_link_update()
7001 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) in bnx2x_ext_phy_hw_reset() argument
7003 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_ext_phy_hw_reset()
7006 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_ext_phy_hw_reset()
7010 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, in bnx2x_save_spirom_version() argument
7017 REG_WR(bp, ver_addr, spirom_ver); in bnx2x_save_spirom_version()
7020 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, in bnx2x_save_bcm_spirom_ver() argument
7026 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7028 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7030 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), in bnx2x_save_bcm_spirom_ver()
7034 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, in bnx2x_ext_phy_10G_an_resolve() argument
7039 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7042 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7058 struct bnx2x *bp = params->bp; in bnx2x_8073_resolve_fc() local
7070 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7074 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7087 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, in bnx2x_8073_8727_external_rom_boot() argument
7097 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7103 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7108 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7113 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7119 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7139 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7142 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7152 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7155 bnx2x_save_bcm_spirom_ver(bp, phy, port); in bnx2x_8073_8727_external_rom_boot()
7168 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_is_snr_needed() argument
7174 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7183 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7194 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_xaui_wa() argument
7198 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7213 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7232 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7250 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_807x_force_10G() argument
7253 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7255 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7257 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7259 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7268 struct bnx2x *bp = params->bp; in bnx2x_8073_set_pause_cl37() local
7269 bnx2x_cl45_read(bp, phy, in bnx2x_8073_set_pause_cl37()
7293 bnx2x_cl45_write(bp, phy, in bnx2x_8073_set_pause_cl37()
7302 struct bnx2x *bp = params->bp; in bnx2x_8073_specific_func() local
7306 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7308 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7318 struct bnx2x *bp = params->bp; in bnx2x_8073_config_init() local
7323 if (CHIP_IS_E2(bp)) in bnx2x_8073_config_init()
7324 gpio_port = BP_PATH(bp); in bnx2x_8073_config_init()
7328 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_config_init()
7331 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_8073_config_init()
7337 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7340 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7350 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7353 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7361 if (REG_RD(bp, params->shmem_base + in bnx2x_8073_config_init()
7366 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7369 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7375 bnx2x_807x_force_10G(bp, phy); in bnx2x_8073_config_init()
7379 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7406 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); in bnx2x_8073_config_init()
7407 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); in bnx2x_8073_config_init()
7414 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7427 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); in bnx2x_8073_config_init()
7430 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); in bnx2x_8073_config_init()
7431 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, in bnx2x_8073_config_init()
7436 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8073_config_init()
7442 if (bnx2x_8073_is_snr_needed(bp, phy)) in bnx2x_8073_config_init()
7443 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7448 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); in bnx2x_8073_config_init()
7450 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); in bnx2x_8073_config_init()
7456 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8073_config_init()
7466 struct bnx2x *bp = params->bp; in bnx2x_8073_read_status() local
7472 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7478 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7480 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7484 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7488 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7494 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7498 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7500 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7507 if (bnx2x_8073_xaui_wa(bp, phy) != 0) in bnx2x_8073_read_status()
7510 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7512 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7516 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7518 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7524 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { in bnx2x_8073_read_status()
7529 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7534 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7538 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7569 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7582 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7587 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_8073_read_status()
7593 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_8073_read_status()
7610 struct bnx2x *bp = params->bp; in bnx2x_8073_link_reset() local
7612 if (CHIP_IS_E2(bp)) in bnx2x_8073_link_reset()
7613 gpio_port = BP_PATH(bp); in bnx2x_8073_link_reset()
7618 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_link_reset()
7630 struct bnx2x *bp = params->bp; in bnx2x_8705_config_init() local
7633 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8705_config_init()
7636 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8705_config_init()
7637 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8705_config_init()
7638 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8705_config_init()
7640 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7642 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7644 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7646 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7649 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); in bnx2x_8705_config_init()
7659 struct bnx2x *bp = params->bp; in bnx2x_8705_read_status() local
7661 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7665 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7669 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7672 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7674 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7693 struct bnx2x *bp = params->bp; in bnx2x_set_disable_pmd_transmit() local
7707 bnx2x_cl45_write(bp, phy, in bnx2x_set_disable_pmd_transmit()
7716 struct bnx2x *bp = params->bp; in bnx2x_get_gpio_port() local
7717 if (CHIP_IS_E2(bp)) in bnx2x_get_gpio_port()
7718 gpio_port = BP_PATH(bp); in bnx2x_get_gpio_port()
7721 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_get_gpio_port()
7722 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_get_gpio_port()
7732 struct bnx2x *bp = params->bp; in bnx2x_sfp_e1e2_set_transmitter() local
7736 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_sfp_e1e2_set_transmitter()
7745 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7755 bnx2x_cl45_write(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7774 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); in bnx2x_sfp_e1e2_set_transmitter()
7787 struct bnx2x *bp = params->bp; in bnx2x_sfp_set_transmitter() local
7789 if (CHIP_IS_E3(bp)) in bnx2x_sfp_set_transmitter()
7800 struct bnx2x *bp = params->bp; in bnx2x_8726_read_sfp_module_eeprom() local
7809 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7814 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7819 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7825 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7844 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7851 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7866 struct bnx2x *bp = params->bp; in bnx2x_warpcore_power_module() local
7868 pin_cfg = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_power_module()
7881 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); in bnx2x_warpcore_power_module()
7893 struct bnx2x *bp = params->bp; in bnx2x_warpcore_read_sfp_module_eeprom() local
7910 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, in bnx2x_warpcore_read_sfp_module_eeprom()
7929 struct bnx2x *bp = params->bp; in bnx2x_8727_read_sfp_module_eeprom() local
7942 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7948 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7954 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7960 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7965 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7971 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7982 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8001 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8008 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8024 struct bnx2x *bp = params->bp; in bnx2x_read_sfp_module_eeprom() local
8065 struct bnx2x *bp = params->bp; in bnx2x_get_edc_mode() local
8131 if (!CHIP_IS_E1x(bp)) { in bnx2x_get_edc_mode()
8132 gport = BP_PATH(bp) + in bnx2x_get_edc_mode()
8135 netdev_err(bp->dev, in bnx2x_get_edc_mode()
8166 media_types = REG_RD(bp, sync_offset); in bnx2x_get_edc_mode()
8178 REG_WR(bp, sync_offset, media_types); in bnx2x_get_edc_mode()
8205 struct bnx2x *bp = params->bp; in bnx2x_verify_sfp_module() local
8211 val = REG_RD(bp, params->shmem_base + in bnx2x_verify_sfp_module()
8241 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); in bnx2x_verify_sfp_module()
8267 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," in bnx2x_verify_sfp_module()
8282 struct bnx2x *bp = params->bp; in bnx2x_wait_for_sfp_module_initialized() local
8310 static void bnx2x_8727_power_module(struct bnx2x *bp, in bnx2x_8727_power_module() argument
8336 bnx2x_cl45_write(bp, phy, in bnx2x_8727_power_module()
8342 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, in bnx2x_8726_set_limiting_mode() argument
8348 bnx2x_cl45_read(bp, phy, in bnx2x_8726_set_limiting_mode()
8357 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8371 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8375 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8379 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8383 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8391 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, in bnx2x_8727_set_limiting_mode() argument
8397 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8402 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8407 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8412 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8417 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8429 struct bnx2x *bp = params->bp; in bnx2x_8727_specific_func() local
8440 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8443 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8446 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8449 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_specific_func()
8460 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8474 struct bnx2x *bp = params->bp; in bnx2x_set_e1e2_module_fault_led() local
8476 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + in bnx2x_set_e1e2_module_fault_led()
8494 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); in bnx2x_set_e1e2_module_fault_led()
8508 struct bnx2x *bp = params->bp; in bnx2x_set_e3_module_fault_led() local
8509 pin_cfg = (REG_RD(bp, params->shmem_base + in bnx2x_set_e3_module_fault_led()
8516 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); in bnx2x_set_e3_module_fault_led()
8522 struct bnx2x *bp = params->bp; in bnx2x_set_sfp_module_fault_led() local
8524 if (CHIP_IS_E3(bp)) { in bnx2x_set_sfp_module_fault_led()
8536 struct bnx2x *bp = params->bp; in bnx2x_warpcore_hw_reset() local
8539 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); in bnx2x_warpcore_hw_reset()
8542 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); in bnx2x_warpcore_hw_reset()
8543 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); in bnx2x_warpcore_hw_reset()
8544 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); in bnx2x_warpcore_hw_reset()
8551 struct bnx2x *bp = params->bp; in bnx2x_power_sfp_module() local
8557 bnx2x_8727_power_module(params->bp, phy, power); in bnx2x_power_sfp_module()
8572 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_limiting_mode() local
8576 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8594 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8597 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8601 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_set_limiting_mode()
8602 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_set_limiting_mode()
8612 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8616 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8627 struct bnx2x *bp = params->bp; in bnx2x_sfp_module_detection() local
8631 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_sfp_module_detection()
8681 struct bnx2x *bp = params->bp; in bnx2x_handle_module_detect_int() local
8685 if (CHIP_IS_E3(bp)) { in bnx2x_handle_module_detect_int()
8692 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, in bnx2x_handle_module_detect_int()
8703 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_handle_module_detect_int()
8707 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_handle_module_detect_int()
8711 bnx2x_set_gpio_int(bp, gpio_num, in bnx2x_handle_module_detect_int()
8716 if (CHIP_IS_E3(bp)) { in bnx2x_handle_module_detect_int()
8722 bnx2x_cl45_read(bp, phy, in bnx2x_handle_module_detect_int()
8729 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_handle_module_detect_int()
8731 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_handle_module_detect_int()
8738 bnx2x_set_gpio_int(bp, gpio_num, in bnx2x_handle_module_detect_int()
8751 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, in bnx2x_sfp_mask_fault() argument
8757 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8760 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8764 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); in bnx2x_sfp_mask_fault()
8769 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); in bnx2x_sfp_mask_fault()
8780 struct bnx2x *bp = params->bp; in bnx2x_8706_8726_read_status() local
8783 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8786 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8706_8726_read_status()
8790 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8792 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8796 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8798 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8800 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8802 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8822 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8824 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8842 struct bnx2x *bp = params->bp; in bnx2x_8706_config_init() local
8844 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8706_config_init()
8847 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8706_config_init()
8848 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8706_config_init()
8849 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8706_config_init()
8853 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8868 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); in bnx2x_8706_config_init()
8875 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); in bnx2x_8706_config_init()
8882 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8885 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8889 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8896 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8900 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8903 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8906 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8910 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8912 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8915 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8919 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8706_config_init()
8925 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8706_config_init()
8932 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8935 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8955 struct bnx2x *bp = params->bp; in bnx2x_8726_config_loopback() local
8957 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); in bnx2x_8726_config_loopback()
8963 struct bnx2x *bp = params->bp; in bnx2x_8726_external_rom_boot() local
8968 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8972 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8977 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8981 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8990 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8995 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8726_external_rom_boot()
9002 struct bnx2x *bp = params->bp; in bnx2x_8726_read_status() local
9006 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_status()
9023 struct bnx2x *bp = params->bp; in bnx2x_8726_config_init() local
9026 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8726_config_init()
9027 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8726_config_init()
9040 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9042 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9044 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9046 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9058 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9060 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9062 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9064 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9066 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9071 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9073 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9078 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9089 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9094 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9107 struct bnx2x *bp = params->bp; in bnx2x_8726_link_reset() local
9110 bnx2x_cl45_write(bp, phy, in bnx2x_8726_link_reset()
9122 struct bnx2x *bp = params->bp; in bnx2x_8727_set_link_led() local
9144 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9150 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9154 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9160 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9172 struct bnx2x *bp = params->bp; in bnx2x_8727_hw_reset() local
9173 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8727_hw_reset()
9174 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8727_hw_reset()
9176 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_8727_hw_reset()
9183 struct bnx2x *bp = params->bp; in bnx2x_8727_config_speed() local
9189 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9191 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9193 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9200 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9204 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9216 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9218 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9224 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9227 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9229 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9231 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9243 struct bnx2x *bp = params->bp; in bnx2x_8727_config_init() local
9246 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8727_config_init()
9254 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9263 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9269 bnx2x_8727_power_module(bp, phy, 1); in bnx2x_8727_config_init()
9271 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9274 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9286 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9290 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9298 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8727_config_init()
9306 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9310 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9312 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9315 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9326 struct bnx2x *bp = params->bp; in bnx2x_8727_handle_mod_abs() local
9328 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_8727_handle_mod_abs()
9332 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9351 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9358 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9376 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9385 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9413 struct bnx2x *bp = params->bp; in bnx2x_8727_read_status() local
9419 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9426 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9432 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8727_read_status()
9435 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9441 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9449 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9454 if (!CHIP_IS_E1x(bp)) in bnx2x_8727_read_status()
9455 oc_port = BP_PATH(bp) + (params->port << 1); in bnx2x_8727_read_status()
9459 netdev_err(bp->dev, "Error: Power fault on Port %d has " in bnx2x_8727_read_status()
9468 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9472 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9477 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9481 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9484 bnx2x_8727_power_module(params->bp, phy, 0); in bnx2x_8727_read_status()
9493 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9506 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9531 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9534 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9550 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9560 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9570 struct bnx2x *bp = params->bp; in bnx2x_8727_link_reset() local
9578 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); in bnx2x_8727_link_reset()
9586 struct bnx2x *bp, in bnx2x_save_848xx_spirom_version() argument
9601 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9602 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, in bnx2x_save_848xx_spirom_version()
9608 bnx2x_cl45_write(bp, phy, reg_set[i].devad, in bnx2x_save_848xx_spirom_version()
9612 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9620 bnx2x_save_spirom_version(bp, port, 0, in bnx2x_save_848xx_spirom_version()
9627 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); in bnx2x_save_848xx_spirom_version()
9628 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); in bnx2x_save_848xx_spirom_version()
9629 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); in bnx2x_save_848xx_spirom_version()
9631 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9639 bnx2x_save_spirom_version(bp, port, 0, in bnx2x_save_848xx_spirom_version()
9645 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9647 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); in bnx2x_save_848xx_spirom_version()
9649 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, in bnx2x_save_848xx_spirom_version()
9654 static void bnx2x_848xx_set_led(struct bnx2x *bp, in bnx2x_848xx_set_led() argument
9668 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_led()
9674 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_led()
9679 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_848xx_set_led()
9689 bnx2x_cl45_read_or_write(bp, phy, in bnx2x_848xx_set_led()
9698 struct bnx2x *bp = params->bp; in bnx2x_848xx_specific_func() local
9704 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848xx_specific_func()
9710 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, in bnx2x_848xx_specific_func()
9713 bnx2x_848xx_set_led(bp, phy); in bnx2x_848xx_specific_func()
9722 struct bnx2x *bp = params->bp; in bnx2x_848xx_cmn_config_init() local
9726 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9730 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9735 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9739 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9758 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9806 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9818 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9824 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9837 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9849 bp, phy, in bnx2x_848xx_cmn_config_init()
9853 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9857 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9869 struct bnx2x *bp = params->bp; in bnx2x_8481_config_init() local
9871 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8481_config_init()
9875 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8481_config_init()
9876 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8481_config_init()
9878 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8481_config_init()
9890 struct bnx2x *bp = params->bp; in bnx2x_84833_cmd_hdlr() local
9892 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9896 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9909 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9913 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9916 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9930 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9934 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9947 struct bnx2x *bp = params->bp; in bnx2x_84833_pair_swap_cfg() local
9950 pair_swap = REG_RD(bp, params->shmem_base + in bnx2x_84833_pair_swap_cfg()
9969 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, in bnx2x_84833_get_reset_gpios() argument
9976 if (CHIP_IS_E3(bp)) { in bnx2x_84833_get_reset_gpios()
9980 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + in bnx2x_84833_get_reset_gpios()
9993 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + in bnx2x_84833_get_reset_gpios()
10010 struct bnx2x *bp = params->bp; in bnx2x_84833_hw_reset_phy() local
10012 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + in bnx2x_84833_hw_reset_phy()
10019 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10022 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10029 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, in bnx2x_84833_hw_reset_phy()
10032 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); in bnx2x_84833_hw_reset_phy()
10045 struct bnx2x *bp = params->bp; in bnx2x_8483x_disable_eee() local
10066 struct bnx2x *bp = params->bp; in bnx2x_8483x_enable_eee() local
10084 struct bnx2x *bp = params->bp; in bnx2x_848x3_config_init() local
10093 if (!(CHIP_IS_E1x(bp))) in bnx2x_848x3_config_init()
10094 port = BP_PATH(bp); in bnx2x_848x3_config_init()
10099 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, in bnx2x_848x3_config_init()
10104 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_config_init()
10109 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_848x3_config_init()
10126 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10134 if (CHIP_IS_E3(bp)) { in bnx2x_848x3_config_init()
10165 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10188 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848x3_config_init()
10191 u32 cms_enable = REG_RD(bp, params->shmem_base + in bnx2x_848x3_config_init()
10196 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10202 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10206 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10238 bnx2x_cl45_read_and_write(bp, phy, in bnx2x_848x3_config_init()
10250 struct bnx2x *bp = params->bp; in bnx2x_848xx_read_status() local
10257 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10259 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10269 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_848xx_read_status()
10274 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_read_status()
10279 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10310 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10317 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10332 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10350 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10360 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10388 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_8481_hw_reset()
10390 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_8481_hw_reset()
10397 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10399 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10406 struct bnx2x *bp = params->bp; in bnx2x_848x3_link_reset() local
10410 if (!(CHIP_IS_E1x(bp))) in bnx2x_848x3_link_reset()
10411 port = BP_PATH(bp); in bnx2x_848x3_link_reset()
10416 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, in bnx2x_848x3_link_reset()
10420 bnx2x_cl45_read(bp, phy, in bnx2x_848x3_link_reset()
10424 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_link_reset()
10433 struct bnx2x *bp = params->bp; in bnx2x_848xx_set_link_led() local
10437 if (!(CHIP_IS_E1x(bp))) in bnx2x_848xx_set_link_led()
10438 port = BP_PATH(bp); in bnx2x_848xx_set_link_led()
10451 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10456 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10461 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10466 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10472 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10487 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10492 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10497 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10502 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10508 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10517 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_848xx_set_link_led()
10524 bp, in bnx2x_848xx_set_link_led()
10529 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10543 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10550 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10556 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10561 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10566 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10571 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10576 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10585 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_848xx_set_link_led()
10592 bp, in bnx2x_848xx_set_link_led()
10597 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10613 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10622 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10629 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10634 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10639 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10644 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10658 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10664 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10670 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10679 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10697 if (CHIP_IS_E3(bp)) { in bnx2x_848xx_set_link_led()
10698 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_848xx_set_link_led()
10710 struct bnx2x *bp = params->bp; in bnx2x_54618se_specific_func() local
10716 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10719 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_specific_func()
10724 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10728 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10739 struct bnx2x *bp = params->bp; in bnx2x_54618se_config_init() local
10752 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_54618se_config_init()
10759 bnx2x_set_cfg_pin(bp, cfg_pin, 1); in bnx2x_54618se_config_init()
10765 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10767 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_54618se_config_init()
10775 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10778 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10782 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10799 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10803 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10807 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10828 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10831 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10867 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10874 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10883 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, in bnx2x_54618se_config_init()
10886 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); in bnx2x_54618se_config_init()
10888 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); in bnx2x_54618se_config_init()
10923 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_54618se_config_init()
10928 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10935 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10945 struct bnx2x *bp = params->bp; in bnx2x_5461x_set_link_led() local
10948 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
10951 bnx2x_cl22_read(bp, phy, in bnx2x_5461x_set_link_led()
10971 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
10981 struct bnx2x *bp = params->bp; in bnx2x_54618se_link_reset() local
10988 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); in bnx2x_54618se_link_reset()
10993 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_54618se_link_reset()
11000 bnx2x_set_cfg_pin(bp, cfg_pin, 0); in bnx2x_54618se_link_reset()
11007 struct bnx2x *bp = params->bp; in bnx2x_54618se_read_status() local
11013 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11019 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11056 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11062 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11076 bnx2x_cl22_read(bp, phy, 0x5, &val); in bnx2x_54618se_read_status()
11094 bnx2x_cl22_read(bp, phy, 0xa, &val); in bnx2x_54618se_read_status()
11113 struct bnx2x *bp = params->bp; in bnx2x_54618se_config_loopback() local
11121 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); in bnx2x_54618se_config_loopback()
11128 bnx2x_cl22_read(bp, phy, 0x00, &val); in bnx2x_54618se_config_loopback()
11131 bnx2x_cl22_write(bp, phy, 0x00, val); in bnx2x_54618se_config_loopback()
11137 bnx2x_cl22_write(bp, phy, 0x18, 7); in bnx2x_54618se_config_loopback()
11138 bnx2x_cl22_read(bp, phy, 0x18, &val); in bnx2x_54618se_config_loopback()
11139 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); in bnx2x_54618se_config_loopback()
11142 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_54618se_config_loopback()
11147 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_54618se_config_loopback()
11156 struct bnx2x *bp = params->bp; in bnx2x_7101_config_loopback() local
11158 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_loopback()
11167 struct bnx2x *bp = params->bp; in bnx2x_7101_config_init() local
11171 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_7101_config_init()
11174 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_7101_config_init()
11175 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_7101_config_init()
11177 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11180 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11185 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11188 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11192 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11195 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11197 bnx2x_save_spirom_version(bp, params->port, in bnx2x_7101_config_init()
11206 struct bnx2x *bp = params->bp; in bnx2x_7101_read_status() local
11209 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11211 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11215 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11217 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11224 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11231 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_7101_read_status()
11255 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_sfx7101_sp_sw_reset() argument
11259 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11266 bnx2x_cl45_write(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11271 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11283 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, in bnx2x_7101_hw_reset()
11286 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_7101_hw_reset()
11294 struct bnx2x *bp = params->bp; in bnx2x_7101_set_link_led() local
11307 bnx2x_cl45_write(bp, phy, in bnx2x_7101_set_link_led()
11812 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, in bnx2x_populate_preemphasis() argument
11824 rx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
11828 tx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
11832 rx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
11836 tx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
11849 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, in bnx2x_get_ext_phy_config() argument
11855 ext_phy_config = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_config()
11860 ext_phy_config = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_config()
11871 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, in bnx2x_populate_int_phy() argument
11876 u32 switch_cfg = (REG_RD(bp, shmem_base + in bnx2x_populate_int_phy()
11880 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_populate_int_phy()
11881 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_populate_int_phy()
11884 if (USES_WARPCORE(bp)) { in bnx2x_populate_int_phy()
11886 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
11889 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) in bnx2x_populate_int_phy()
11894 serdes_net_if = (REG_RD(bp, shmem_base + in bnx2x_populate_int_phy()
11969 if (CHIP_REV(bp) == CHIP_REV_Ax) in bnx2x_populate_int_phy()
11976 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
11982 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
11993 phy->mdio_ctrl = bnx2x_get_emac_base(bp, in bnx2x_populate_int_phy()
11996 if (CHIP_IS_E2(bp)) in bnx2x_populate_int_phy()
12004 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); in bnx2x_populate_int_phy()
12008 static int bnx2x_populate_ext_phy(struct bnx2x *bp, in bnx2x_populate_ext_phy() argument
12017 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, in bnx2x_populate_ext_phy()
12081 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); in bnx2x_populate_ext_phy()
12087 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, in bnx2x_populate_ext_phy()
12098 u32 size = REG_RD(bp, shmem2_base); in bnx2x_populate_ext_phy()
12113 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); in bnx2x_populate_ext_phy()
12121 u32 raw_ver = REG_RD(bp, phy->ver_addr); in bnx2x_populate_ext_phy()
12135 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, in bnx2x_populate_phy() argument
12141 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); in bnx2x_populate_phy()
12142 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_populate_phy()
12151 struct bnx2x *bp = params->bp; in bnx2x_phy_def_cfg() local
12155 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12158 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12163 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12166 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12256 struct bnx2x *bp = params->bp; in bnx2x_phy_probe() local
12276 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, in bnx2x_phy_probe()
12302 media_types = REG_RD(bp, sync_offset); in bnx2x_phy_probe()
12316 REG_WR(bp, sync_offset, media_types); in bnx2x_phy_probe()
12329 struct bnx2x *bp = params->bp; in bnx2x_init_bmac_loopback() local
12343 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_bmac_loopback()
12349 struct bnx2x *bp = params->bp; in bnx2x_init_emac_loopback() local
12362 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_emac_loopback()
12368 struct bnx2x *bp = params->bp; in bnx2x_init_xmac_loopback() local
12382 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); in bnx2x_init_xmac_loopback()
12388 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xmac_loopback()
12394 struct bnx2x *bp = params->bp; in bnx2x_init_umac_loopback() local
12403 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_umac_loopback()
12409 struct bnx2x *bp = params->bp; in bnx2x_init_xgxs_loopback() local
12422 if (!USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12427 if (USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12434 if (USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12453 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xgxs_loopback()
12460 struct bnx2x *bp = params->bp; in bnx2x_set_rx_filter() local
12464 if (!CHIP_IS_E1x(bp)) in bnx2x_set_rx_filter()
12466 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in bnx2x_set_rx_filter()
12468 if (!CHIP_IS_E1(bp)) { in bnx2x_set_rx_filter()
12469 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in bnx2x_set_rx_filter()
12473 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_set_rx_filter()
12481 struct bnx2x *bp = params->bp; in bnx2x_avoid_link_flap() local
12483 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_avoid_link_flap()
12503 lfa_sts = REG_RD(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12510 if (CHIP_IS_E3(bp)) { in bnx2x_avoid_link_flap()
12512 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12516 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12540 REG_WR(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12544 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_avoid_link_flap()
12556 struct bnx2x *bp = params->bp; in bnx2x_cannot_avoid_link_flap() local
12563 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12567 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12571 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12576 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12582 tmp_val = REG_RD(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12587 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12590 lfa_sts = REG_RD(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12606 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12614 struct bnx2x *bp = params->bp; in bnx2x_phy_init() local
12646 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in bnx2x_phy_init()
12682 if (!CHIP_IS_E3(bp)) { in bnx2x_phy_init()
12686 bnx2x_serdes_deassert(bp, params->port); in bnx2x_phy_init()
12702 struct bnx2x *bp = params->bp; in bnx2x_link_reset() local
12711 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, in bnx2x_link_reset()
12718 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_link_reset()
12721 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12722 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12723 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12726 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12727 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); in bnx2x_link_reset()
12733 if (!CHIP_IS_E3(bp)) in bnx2x_link_reset()
12734 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_reset()
12741 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_link_reset()
12762 bnx2x_rearm_latch_signal(bp, port, 0); in bnx2x_link_reset()
12763 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, in bnx2x_link_reset()
12771 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12773 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_link_reset()
12775 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
12776 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
12780 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_link_reset()
12782 REG_WR(bp, xmac_base + XMAC_REG_CTRL, in bnx2x_link_reset()
12792 struct bnx2x *bp = params->bp; in bnx2x_lfa_reset() local
12802 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_lfa_reset()
12808 if (!CHIP_IS_E3(bp)) in bnx2x_lfa_reset()
12809 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_lfa_reset()
12811 if (CHIP_IS_E3(bp)) { in bnx2x_lfa_reset()
12829 if (!CHIP_IS_E3(bp)) in bnx2x_lfa_reset()
12830 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); in bnx2x_lfa_reset()
12832 if (CHIP_IS_E3(bp)) { in bnx2x_lfa_reset()
12837 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_lfa_reset()
12844 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, in bnx2x_8073_common_init_phy() argument
12855 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8073_common_init_phy()
12856 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8073_common_init_phy()
12858 bnx2x_ext_phy_hw_reset(bp, port); in bnx2x_8073_common_init_phy()
12863 if (CHIP_IS_E1x(bp)) { in bnx2x_8073_common_init_phy()
12874 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8073_common_init_phy()
12881 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_8073_common_init_phy()
12891 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_common_init_phy()
12896 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8073_common_init_phy()
12915 if (CHIP_IS_E1x(bp)) in bnx2x_8073_common_init_phy()
12922 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12927 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12932 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12947 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12951 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12957 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12960 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12965 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_common_init_phy()
12970 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, in bnx2x_8726_common_init_phy() argument
12980 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); in bnx2x_8726_common_init_phy()
12983 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_8726_common_init_phy()
12985 bnx2x_ext_phy_hw_reset(bp, 0); in bnx2x_8726_common_init_phy()
12991 if (CHIP_IS_E1x(bp)) { in bnx2x_8726_common_init_phy()
12999 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8726_common_init_phy()
13007 bnx2x_cl45_write(bp, &phy, in bnx2x_8726_common_init_phy()
13012 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, in bnx2x_8726_common_init_phy()
13019 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, in bnx2x_get_ext_phy_reset_gpio() argument
13023 u32 phy_gpio_reset = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_reset_gpio()
13065 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, in bnx2x_8727_common_init_phy() argument
13075 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8727_common_init_phy()
13076 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8727_common_init_phy()
13084 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], in bnx2x_8727_common_init_phy()
13091 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, in bnx2x_8727_common_init_phy()
13094 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, in bnx2x_8727_common_init_phy()
13104 if (CHIP_IS_E1x(bp)) { in bnx2x_8727_common_init_phy()
13115 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8727_common_init_phy()
13122 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_8727_common_init_phy()
13131 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8727_common_init_phy()
13146 if (CHIP_IS_E1x(bp)) in bnx2x_8727_common_init_phy()
13152 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], in bnx2x_8727_common_init_phy()
13156 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8727_common_init_phy()
13164 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, in bnx2x_84833_common_init_phy() argument
13171 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); in bnx2x_84833_common_init_phy()
13172 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); in bnx2x_84833_common_init_phy()
13174 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); in bnx2x_84833_common_init_phy()
13180 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], in bnx2x_ext_phy_common_init() argument
13188 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13195 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13204 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13213 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13228 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_ext_phy_common_init()
13234 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], in bnx2x_common_init_phy() argument
13242 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); in bnx2x_common_init_phy()
13243 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); in bnx2x_common_init_phy()
13245 if (CHIP_IS_E3(bp)) { in bnx2x_common_init_phy()
13247 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); in bnx2x_common_init_phy()
13248 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); in bnx2x_common_init_phy()
13251 phy_ver = REG_RD(bp, shmem_base_path[0] + in bnx2x_common_init_phy()
13263 ext_phy_config = bnx2x_get_ext_phy_config(bp, in bnx2x_common_init_phy()
13267 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, in bnx2x_common_init_phy()
13278 struct bnx2x *bp = params->bp; in bnx2x_check_over_curr() local
13283 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_check_over_curr()
13290 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) in bnx2x_check_over_curr()
13295 netdev_err(bp->dev, "Error: Power fault on Port %d has" in bnx2x_check_over_curr()
13315 struct bnx2x *bp = params->bp; in bnx2x_analyze_link_error() local
13351 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_analyze_link_error()
13364 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_analyze_link_error()
13376 bnx2x_notify_link_changed(bp); in bnx2x_analyze_link_error()
13394 struct bnx2x *bp = params->bp; in bnx2x_check_half_open_conn() local
13399 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) in bnx2x_check_half_open_conn()
13402 if (CHIP_IS_E3(bp) && in bnx2x_check_half_open_conn()
13403 (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_check_half_open_conn()
13413 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13414 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
13417 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) in bnx2x_check_half_open_conn()
13423 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_check_half_open_conn()
13431 if (CHIP_IS_E2(bp)) in bnx2x_check_half_open_conn()
13436 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); in bnx2x_check_half_open_conn()
13449 struct bnx2x *bp = params->bp; in bnx2x_sfp_tx_fault_detection() local
13454 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, in bnx2x_sfp_tx_fault_detection()
13459 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { in bnx2x_sfp_tx_fault_detection()
13492 struct bnx2x *bp = params->bp; in bnx2x_kr2_recovery() local
13502 struct bnx2x *bp = params->bp; in bnx2x_check_kr2_wa() local
13526 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_check_kr2_wa()
13528 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13530 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13574 struct bnx2x *bp = params->bp; in bnx2x_period_func() local
13585 if (CHIP_IS_E3(bp)) { in bnx2x_period_func()
13595 if ((REG_RD(bp, params->shmem_base + in bnx2x_period_func()
13614 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, in bnx2x_fan_failure_det_req() argument
13623 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_fan_failure_det_req()
13638 struct bnx2x *bp = params->bp; in bnx2x_hw_reset_phy() local
13640 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in bnx2x_hw_reset_phy()
13657 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, in bnx2x_init_mod_abs_int() argument
13664 if (CHIP_IS_E3(bp)) { in bnx2x_init_mod_abs_int()
13665 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, in bnx2x_init_mod_abs_int()
13675 if (bnx2x_populate_phy(bp, phy_index, shmem_base, in bnx2x_init_mod_abs_int()
13693 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); in bnx2x_init_mod_abs_int()
13695 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_init_mod_abs_int()
13696 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_init_mod_abs_int()
13705 REG_WR(bp, sync_offset, vars->aeu_int_mask); in bnx2x_init_mod_abs_int()
13716 aeu_mask = REG_RD(bp, offset); in bnx2x_init_mod_abs_int()
13718 REG_WR(bp, offset, aeu_mask); in bnx2x_init_mod_abs_int()
13721 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); in bnx2x_init_mod_abs_int()
13723 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_init_mod_abs_int()