191 	u32 cr;  in axienet_dma_bd_init()  local
240 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_dma_bd_init()
242 	cr = ((cr & ~XAXIDMA_COALESCE_MASK) |  in axienet_dma_bd_init()
245 	cr = ((cr & ~XAXIDMA_DELAY_MASK) |  in axienet_dma_bd_init()
248 	cr |= XAXIDMA_IRQ_ALL_MASK;  in axienet_dma_bd_init()
250 	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);  in axienet_dma_bd_init()
253 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_dma_bd_init()
255 	cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |  in axienet_dma_bd_init()
258 	cr = (((cr & ~XAXIDMA_DELAY_MASK)) |  in axienet_dma_bd_init()
261 	cr |= XAXIDMA_IRQ_ALL_MASK;  in axienet_dma_bd_init()
263 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);  in axienet_dma_bd_init()
268 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_dma_bd_init()
270 			  cr | XAXIDMA_CR_RUNSTOP_MASK);  in axienet_dma_bd_init()
278 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_dma_bd_init()
280 			  cr | XAXIDMA_CR_RUNSTOP_MASK);  in axienet_dma_bd_init()
804 	u32 cr;  in axienet_tx_irq()  local
821 		cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_tx_irq()
823 		cr &= (~XAXIDMA_IRQ_ALL_MASK);  in axienet_tx_irq()
825 		axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);  in axienet_tx_irq()
827 		cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_tx_irq()
829 		cr &= (~XAXIDMA_IRQ_ALL_MASK);  in axienet_tx_irq()
831 		axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);  in axienet_tx_irq()
852 	u32 cr;  in axienet_rx_irq()  local
869 		cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_rx_irq()
871 		cr &= (~XAXIDMA_IRQ_ALL_MASK);  in axienet_rx_irq()
873 		axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);  in axienet_rx_irq()
875 		cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_rx_irq()
877 		cr &= (~XAXIDMA_IRQ_ALL_MASK);  in axienet_rx_irq()
879 		axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);  in axienet_rx_irq()
976 	u32 cr;  in axienet_stop()  local
981 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_stop()
983 			  cr & (~XAXIDMA_CR_RUNSTOP_MASK));  in axienet_stop()
984 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_stop()
986 			  cr & (~XAXIDMA_CR_RUNSTOP_MASK));  in axienet_stop()
1344 	u32 cr, i;  in axienet_dma_err_handler()  local
1402 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_dma_err_handler()
1404 	cr = ((cr & ~XAXIDMA_COALESCE_MASK) |  in axienet_dma_err_handler()
1407 	cr = ((cr & ~XAXIDMA_DELAY_MASK) |  in axienet_dma_err_handler()
1410 	cr |= XAXIDMA_IRQ_ALL_MASK;  in axienet_dma_err_handler()
1412 	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);  in axienet_dma_err_handler()
1415 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_dma_err_handler()
1417 	cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |  in axienet_dma_err_handler()
1420 	cr = (((cr & ~XAXIDMA_DELAY_MASK)) |  in axienet_dma_err_handler()
1423 	cr |= XAXIDMA_IRQ_ALL_MASK;  in axienet_dma_err_handler()
1425 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);  in axienet_dma_err_handler()
1430 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_dma_err_handler()
1432 			  cr | XAXIDMA_CR_RUNSTOP_MASK);  in axienet_dma_err_handler()
1440 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_dma_err_handler()
1442 			  cr | XAXIDMA_CR_RUNSTOP_MASK);  in axienet_dma_err_handler()