Lines Matching refs:ON
467 EnTXFIFOUnderrunEOMInt(iobase, ON); in via_hw_init()
475 EnRXSpecInt(iobase, ON); in via_hw_init()
489 SIRFilter(iobase, ON); in via_hw_init()
490 SetSIR(iobase, ON); in via_hw_init()
491 CRC16(iobase, ON); in via_hw_init()
539 UseOneRX(iobase, ON); // use one RX pin RX1,RX2 in via_ircc_change_dongle_speed()
543 EnRX2(iobase, ON); //sir to rx2 in via_ircc_change_dongle_speed()
548 SlowIRRXLowActive(iobase, ON); in via_ircc_change_dongle_speed()
567 UseOneRX(iobase, ON); //use ONE RX....RX1 in via_ircc_change_dongle_speed()
571 EnRX2(iobase, ON); in via_ircc_change_dongle_speed()
575 SlowIRRXLowActive(iobase, ON); in via_ircc_change_dongle_speed()
585 SlowIRRXLowActive(iobase, ON); in via_ircc_change_dongle_speed()
591 WriteTX(iobase, ON); in via_ircc_change_dongle_speed()
594 SlowIRRXLowActive(iobase, ON); in via_ircc_change_dongle_speed()
622 UseOneRX(iobase, ON); //use ONE RX....RX1 in via_ircc_change_dongle_speed()
624 InvertRX(iobase, ON); // invert RX pin in via_ircc_change_dongle_speed()
626 EnRX2(iobase, ON); //sir to rx2 in via_ircc_change_dongle_speed()
632 SlowIRRXLowActive(iobase, ON); in via_ircc_change_dongle_speed()
688 SetSIR(iobase, ON); in via_ircc_change_speed()
689 CRC16(iobase, ON); in via_ircc_change_speed()
695 SetSIR(iobase, ON); in via_ircc_change_speed()
696 CRC16(iobase, ON); in via_ircc_change_speed()
700 SetMIR(iobase, ON); in via_ircc_change_speed()
705 SetFIR(iobase, ON); in via_ircc_change_speed()
709 EnTXCRC(iobase, ON); in via_ircc_change_speed()
713 SetVFIR(iobase, ON); in via_ircc_change_speed()
741 SIRFilter(iobase, ON); in via_ircc_change_speed()
742 SIRRecvAny(iobase, ON); in via_ircc_change_speed()
792 SIRFilter(iobase, ON); in via_ircc_hard_xmit_sir()
793 SetSIR(iobase, ON); in via_ircc_hard_xmit_sir()
794 CRC16(iobase, ON); in via_ircc_hard_xmit_sir()
811 EnableTX(iobase, ON); in via_ircc_hard_xmit_sir()
820 EnAllInt(iobase, ON); in via_ircc_hard_xmit_sir()
821 EnTXDMA(iobase, ON); in via_ircc_hard_xmit_sir()
829 TXStart(iobase, ON); in via_ircc_hard_xmit_sir()
890 EnPhys(iobase, ON); in via_ircc_dma_xmit()
891 EnableTX(iobase, ON); in via_ircc_dma_xmit()
898 EnAllInt(iobase, ON); in via_ircc_dma_xmit()
899 EnTXDMA(iobase, ON); in via_ircc_dma_xmit()
912 TXStart(iobase, ON); in via_ircc_dma_xmit()
1008 EnPhys(iobase, ON); in via_ircc_dma_receive()
1010 EnableRX(iobase, ON); in via_ircc_dma_receive()
1018 EnAllInt(iobase, ON); in via_ircc_dma_receive()
1020 EnRXDMA(iobase, ON); in via_ircc_dma_receive()
1024 RXStart(iobase, ON); in via_ircc_dma_receive()
1194 RXStart(iobase, ON); in upload_rxdata()
1417 SIRFilter(iobase, ON); in hwreset()
1418 SetSIR(iobase, ON); in hwreset()
1419 CRC16(iobase, ON); in hwreset()
1502 EnAllInt(iobase, ON); in via_ircc_net_open()