279 		struct { u32 data32; };  member
286 		struct { u32 data32; };
380 		msg.data32 >>= 2;  in hss_config_set_lut()
381 		msg.data32 |= TDMMAP_HDLC << 30;  in hss_config_set_lut()
401 	msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |  in hss_config()
404 		msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;  in hss_config()
408 	msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;  in hss_config()
415 	msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |  in hss_config()
423 	msg.data32 = port->clock_reg;  in hss_config()
451 	    msg.cmd != PORT_CONFIG_LOAD || msg.data32) {  in hss_config()
485 	return msg.data32;  in hss_get_status()
495 	msg.data32 = 0;  in hss_start_hdlc()
545 	msg.data32 = 0x7F7F7F7F; /* ??? FIXME */  in hss_load_firmware()