Lines Matching refs:ah
49 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) in ar5008_write_bank6() argument
51 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
52 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
55 ENABLE_REGWRITE_BUFFER(ah); in ar5008_write_bank6()
58 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
62 REGWRITE_BUFFER_FLUSH(ah); in ar5008_write_bank6()
129 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) in ar5008_hw_force_bias() argument
131 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_force_bias()
136 if (!AR_SREV_5416(ah) || synth_freq >= 3000) in ar5008_hw_force_bias()
139 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); in ar5008_hw_force_bias()
155 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); in ar5008_hw_force_bias()
158 ar5008_write_bank6(ah, ®_writes); in ar5008_hw_force_bias()
170 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar5008_hw_set_channel() argument
172 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_set_channel()
180 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar5008_hw_set_channel()
200 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
203 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
217 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_set_channel()
229 ar5008_hw_force_bias(ah, freq); in ar5008_hw_set_channel()
235 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
237 ah->curchan = chan; in ar5008_hw_set_channel()
250 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, in ar5008_hw_spur_mitigate() argument
282 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); in ar5008_hw_spur_mitigate()
297 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
303 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
310 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
321 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
339 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_spur_mitigate()
340 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_spur_mitigate()
373 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_spur_mitigate()
374 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_spur_mitigate()
384 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_spur_mitigate()
385 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_spur_mitigate()
395 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ar5008_hw_spur_mitigate()
396 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ar5008_hw_spur_mitigate()
406 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ar5008_hw_spur_mitigate()
407 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ar5008_hw_spur_mitigate()
417 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ar5008_hw_spur_mitigate()
418 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ar5008_hw_spur_mitigate()
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ar5008_hw_spur_mitigate()
429 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ar5008_hw_spur_mitigate()
439 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ar5008_hw_spur_mitigate()
440 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ar5008_hw_spur_mitigate()
450 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ar5008_hw_spur_mitigate()
451 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ar5008_hw_spur_mitigate()
460 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) in ar5008_hw_rf_alloc_ext_banks() argument
462 int size = ah->iniBank6.ia_rows * sizeof(u32); in ar5008_hw_rf_alloc_ext_banks()
464 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_rf_alloc_ext_banks()
467 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); in ar5008_hw_rf_alloc_ext_banks()
468 if (!ah->analogBank6Data) in ar5008_hw_rf_alloc_ext_banks()
487 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, in ar5008_hw_set_rf_regs() argument
502 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_set_rf_regs()
506 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); in ar5008_hw_set_rf_regs()
508 for (i = 0; i < ah->iniBank6.ia_rows; i++) in ar5008_hw_set_rf_regs()
509 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); in ar5008_hw_set_rf_regs()
514 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); in ar5008_hw_set_rf_regs()
515 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); in ar5008_hw_set_rf_regs()
516 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
518 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
521 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); in ar5008_hw_set_rf_regs()
522 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); in ar5008_hw_set_rf_regs()
523 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
525 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
535 ar5008_write_bank6(ah, ®Writes); in ar5008_hw_set_rf_regs()
541 static void ar5008_hw_init_bb(struct ath_hw *ah, in ar5008_hw_init_bb() argument
546 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
548 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar5008_hw_init_bb()
550 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar5008_hw_init_bb()
553 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) in ar5008_hw_init_chain_masks() argument
557 rx_chainmask = ah->rxchainmask; in ar5008_hw_init_chain_masks()
558 tx_chainmask = ah->txchainmask; in ar5008_hw_init_chain_masks()
563 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
566 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { in ar5008_hw_init_chain_masks()
567 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
568 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
574 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_init_chain_masks()
575 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
576 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
579 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_init_chain_masks()
583 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); in ar5008_hw_init_chain_masks()
585 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_init_chain_masks()
588 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
591 if (AR_SREV_9100(ah)) in ar5008_hw_init_chain_masks()
592 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
593 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
596 static void ar5008_hw_override_ini(struct ath_hw *ah, in ar5008_hw_override_ini() argument
606 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
608 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar5008_hw_override_ini()
616 val = REG_READ(ah, AR_PCU_MISC_MODE2) & in ar5008_hw_override_ini()
619 if (!AR_SREV_9271(ah)) in ar5008_hw_override_ini()
622 if (AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_override_ini()
627 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar5008_hw_override_ini()
630 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_override_ini()
636 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); in ar5008_hw_override_ini()
642 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { in ar5008_hw_override_ini()
643 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
645 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); in ar5008_hw_override_ini()
649 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, in ar5008_hw_set_channel_regs() argument
655 if (AR_SREV_9285_12_OR_LATER(ah)) in ar5008_hw_set_channel_regs()
656 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
669 REG_WRITE(ah, AR_PHY_TURBO, phymode); in ar5008_hw_set_channel_regs()
671 ath9k_hw_set11nmac2040(ah, chan); in ar5008_hw_set_channel_regs()
673 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_set_channel_regs()
675 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
676 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
678 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_set_channel_regs()
682 static int ar5008_hw_process_ini(struct ath_hw *ah, in ar5008_hw_process_ini() argument
685 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_process_ini()
701 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5008_hw_process_ini()
704 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); in ar5008_hw_process_ini()
705 if (ah->eep_ops->set_addac) in ar5008_hw_process_ini()
706 ah->eep_ops->set_addac(ah, chan); in ar5008_hw_process_ini()
708 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); in ar5008_hw_process_ini()
709 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ar5008_hw_process_ini()
711 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_process_ini()
713 for (i = 0; i < ah->iniModes.ia_rows; i++) { in ar5008_hw_process_ini()
714 u32 reg = INI_RA(&ah->iniModes, i, 0); in ar5008_hw_process_ini()
715 u32 val = INI_RA(&ah->iniModes, i, modesIndex); in ar5008_hw_process_ini()
717 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) in ar5008_hw_process_ini()
720 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
723 && ah->config.analog_shiftreg in ar5008_hw_process_ini()
731 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_process_ini()
733 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
734 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); in ar5008_hw_process_ini()
736 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || in ar5008_hw_process_ini()
737 AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
738 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar5008_hw_process_ini()
740 if (AR_SREV_9271_10(ah)) { in ar5008_hw_process_ini()
741 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); in ar5008_hw_process_ini()
742 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); in ar5008_hw_process_ini()
745 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_process_ini()
748 for (i = 0; i < ah->iniCommon.ia_rows; i++) { in ar5008_hw_process_ini()
749 u32 reg = INI_RA(&ah->iniCommon, i, 0); in ar5008_hw_process_ini()
750 u32 val = INI_RA(&ah->iniCommon, i, 1); in ar5008_hw_process_ini()
752 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
755 && ah->config.analog_shiftreg in ar5008_hw_process_ini()
763 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_process_ini()
765 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); in ar5008_hw_process_ini()
767 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar5008_hw_process_ini()
768 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, in ar5008_hw_process_ini()
771 ar5008_hw_override_ini(ah, chan); in ar5008_hw_process_ini()
772 ar5008_hw_set_channel_regs(ah, chan); in ar5008_hw_process_ini()
773 ar5008_hw_init_chain_masks(ah); in ar5008_hw_process_ini()
774 ath9k_olc_init(ah); in ar5008_hw_process_ini()
775 ath9k_hw_apply_txpower(ah, chan, false); in ar5008_hw_process_ini()
778 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { in ar5008_hw_process_ini()
779 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); in ar5008_hw_process_ini()
786 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) in ar5008_hw_set_rfmode() argument
798 if (!AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_set_rfmode()
802 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar5008_hw_set_rfmode()
805 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5008_hw_set_rfmode()
808 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) in ar5008_hw_mark_phy_inactive() argument
810 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar5008_hw_mark_phy_inactive()
813 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, in ar5008_hw_set_delta_slope() argument
825 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar5008_hw_set_delta_slope()
828 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar5008_hw_set_delta_slope()
831 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5008_hw_set_delta_slope()
833 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5008_hw_set_delta_slope()
838 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar5008_hw_set_delta_slope()
841 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5008_hw_set_delta_slope()
843 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5008_hw_set_delta_slope()
847 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) in ar5008_hw_rfbus_req() argument
849 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar5008_hw_rfbus_req()
850 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar5008_hw_rfbus_req()
854 static void ar5008_hw_rfbus_done(struct ath_hw *ah) in ar5008_hw_rfbus_done() argument
856 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
858 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar5008_hw_rfbus_done()
860 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar5008_hw_rfbus_done()
863 static void ar5008_restore_chainmask(struct ath_hw *ah) in ar5008_restore_chainmask() argument
865 int rx_chainmask = ah->rxchainmask; in ar5008_restore_chainmask()
868 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
869 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
873 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, in ar9160_hw_compute_pll_control() argument
893 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, in ar5008_hw_compute_pll_control() argument
913 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, in ar5008_hw_ani_control_new() argument
917 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_ani_control_new()
918 struct ath9k_channel *chan = ah->curchan; in ar5008_hw_ani_control_new()
919 struct ar5416AniState *aniState = &ah->ani; in ar5008_hw_ani_control_new()
922 switch (cmd & ah->ani_function) { in ar5008_hw_ani_control_new()
957 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
960 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
963 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
965 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
967 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
969 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
973 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
975 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
977 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
979 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
983 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
986 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
997 ah->stats.ast_ani_ofdmon++; in ar5008_hw_ani_control_new()
999 ah->stats.ast_ani_ofdmoff++; in ar5008_hw_ani_control_new()
1008 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar5008_hw_ani_control_new()
1010 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar5008_hw_ani_control_new()
1031 ah->stats.ast_ani_stepup++; in ar5008_hw_ani_control_new()
1033 ah->stats.ast_ani_stepdown++; in ar5008_hw_ani_control_new()
1042 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar5008_hw_ani_control_new()
1045 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar5008_hw_ani_control_new()
1066 ah->stats.ast_ani_spurup++; in ar5008_hw_ani_control_new()
1068 ah->stats.ast_ani_spurdown++; in ar5008_hw_ani_control_new()
1097 static void ar5008_hw_do_getnf(struct ath_hw *ah, in ar5008_hw_do_getnf() argument
1102 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1105 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
1108 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); in ar5008_hw_do_getnf()
1111 if (!IS_CHAN_HT40(ah->curchan)) in ar5008_hw_do_getnf()
1114 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1117 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1120 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1129 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar5008_hw_ani_cache_ini_regs() argument
1131 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_ani_cache_ini_regs()
1132 struct ath9k_channel *chan = ah->curchan; in ar5008_hw_ani_cache_ini_regs()
1133 struct ar5416AniState *aniState = &ah->ani; in ar5008_hw_ani_cache_ini_regs()
1140 ah->hw_version.macVersion, in ar5008_hw_ani_cache_ini_regs()
1141 ah->hw_version.macRev, in ar5008_hw_ani_cache_ini_regs()
1142 ah->opmode, in ar5008_hw_ani_cache_ini_regs()
1145 val = REG_READ(ah, AR_PHY_SFCORR); in ar5008_hw_ani_cache_ini_regs()
1150 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar5008_hw_ani_cache_ini_regs()
1155 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar5008_hw_ani_cache_ini_regs()
1160 iniDef->firstep = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1163 iniDef->firstepLow = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1166 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1169 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1180 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) in ar5008_hw_set_nf_limits() argument
1182 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1183 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1184 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1185 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1186 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1187 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1190 static void ar5008_hw_set_radar_params(struct ath_hw *ah, in ar5008_hw_set_radar_params() argument
1196 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar5008_hw_set_radar_params()
1213 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar5008_hw_set_radar_params()
1214 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar5008_hw_set_radar_params()
1216 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
1218 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
1221 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) in ar5008_hw_set_radar_conf() argument
1223 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar5008_hw_set_radar_conf()
1235 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) in ar5008_hw_attach_phy_ops() argument
1237 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar5008_hw_attach_phy_ops()
1248 ret = ar5008_hw_rf_alloc_ext_banks(ah); in ar5008_hw_attach_phy_ops()
1271 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_attach_phy_ops()
1276 ar5008_hw_set_nf_limits(ah); in ar5008_hw_attach_phy_ops()
1277 ar5008_hw_set_radar_conf(ah); in ar5008_hw_attach_phy_ops()
1278 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); in ar5008_hw_attach_phy_ops()