Lines Matching refs:ah
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_set_channel() argument
75 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_channel()
79 if (AR_SREV_9330(ah)) { in ar9003_hw_set_channel()
80 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_channel()
98 } else if (AR_SREV_9340(ah)) { in ar9003_hw_set_channel()
99 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
106 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { in ar9003_hw_set_channel()
107 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) && in ar9003_hw_set_channel()
122 ah->is_clk_25mhz) { in ar9003_hw_set_channel()
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, in ar9003_hw_set_channel()
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
158 ah->curchan = chan; in ar9003_hw_set_channel()
173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, in ar9003_hw_spur_mitigate_mrc_cck() argument
180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); in ar9003_hw_spur_mitigate_mrc_cck()
187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
188 AR_SREV_9550(ah)) { in ar9003_hw_spur_mitigate_mrc_cck()
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_mrc_cck()
204 range = AR_SREV_9462(ah) ? 5 : 10; in ar9003_hw_spur_mitigate_mrc_cck()
210 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) in ar9003_hw_spur_mitigate_mrc_cck()
214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
215 AR_SREV_9550(ah)) in ar9003_hw_spur_mitigate_mrc_cck()
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) in ar9003_hw_spur_ofdm_clear() argument
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm_clear()
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm_clear()
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm_clear()
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, in ar9003_hw_spur_ofdm() argument
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm()
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) in ar9003_hw_spur_ofdm()
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
337 if (!AR_SREV_9340(ah) && in ar9003_hw_spur_ofdm()
338 REG_READ_FIELD(ah, AR_PHY_MODE, in ar9003_hw_spur_ofdm()
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm()
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm()
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, in ar9003_hw_spur_ofdm_9565() argument
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, in ar9003_hw_spur_ofdm_9565()
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, in ar9003_hw_spur_ofdm_9565()
404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, in ar9003_hw_spur_ofdm_work() argument
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
446 ar9003_hw_spur_ofdm(ah, in ar9003_hw_spur_ofdm_work()
455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, in ar9003_hw_spur_mitigate_ofdm() argument
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_spur_mitigate_ofdm()
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_ofdm()
490 ar9003_hw_spur_ofdm_clear(ah); in ar9003_hw_spur_mitigate_ofdm()
496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, in ar9003_hw_spur_mitigate_ofdm()
499 if (AR_SREV_9565(ah) && (i < 4)) { in ar9003_hw_spur_mitigate_ofdm()
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset); in ar9003_hw_spur_mitigate_ofdm()
512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, in ar9003_hw_spur_mitigate() argument
515 if (!AR_SREV_9565(ah)) in ar9003_hw_spur_mitigate()
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); in ar9003_hw_spur_mitigate()
517 ar9003_hw_spur_mitigate_ofdm(ah, chan); in ar9003_hw_spur_mitigate()
520 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, in ar9003_hw_compute_pll_control_soc() argument
537 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, in ar9003_hw_compute_pll_control() argument
554 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, in ar9003_hw_set_channel_regs() argument
561 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
577 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
581 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); in ar9003_hw_set_channel_regs()
584 ath9k_hw_set11nmac2040(ah, chan); in ar9003_hw_set_channel_regs()
587 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
589 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
592 static void ar9003_hw_init_bb(struct ath_hw *ah, in ar9003_hw_init_bb() argument
602 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
605 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_bb()
606 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar9003_hw_init_bb()
609 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) in ar9003_hw_set_chain_masks() argument
611 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) in ar9003_hw_set_chain_masks()
612 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
615 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
616 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
618 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
621 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
627 static void ar9003_hw_override_ini(struct ath_hw *ah) in ar9003_hw_override_ini() argument
636 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
645 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
649 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar9003_hw_override_ini()
651 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_override_ini()
652 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, in ar9003_hw_override_ini()
655 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_override_ini()
657 ah->enabled_cals |= TX_IQ_CAL; in ar9003_hw_override_ini()
659 ah->enabled_cals &= ~TX_IQ_CAL; in ar9003_hw_override_ini()
663 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
664 ah->enabled_cals |= TX_CL_CAL; in ar9003_hw_override_ini()
666 ah->enabled_cals &= ~TX_CL_CAL; in ar9003_hw_override_ini()
668 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) { in ar9003_hw_override_ini()
669 if (ah->is_clk_25mhz) { in ar9003_hw_override_ini()
670 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); in ar9003_hw_override_ini()
671 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); in ar9003_hw_override_ini()
672 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); in ar9003_hw_override_ini()
674 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); in ar9003_hw_override_ini()
675 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); in ar9003_hw_override_ini()
676 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); in ar9003_hw_override_ini()
682 static void ar9003_hw_prog_ini(struct ath_hw *ah, in ar9003_hw_prog_ini() argument
704 REG_WRITE(ah, reg, val); in ar9003_hw_prog_ini()
710 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9550_hw_get_modes_txgain_index() argument
735 static void ar9003_doubler_fix(struct ath_hw *ah) in ar9003_doubler_fix() argument
737 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { in ar9003_doubler_fix()
738 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
741 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
744 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
750 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
752 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
754 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
759 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
761 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
763 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
768 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, in ar9003_doubler_fix()
771 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, in ar9003_doubler_fix()
774 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, in ar9003_doubler_fix()
777 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, in ar9003_doubler_fix()
783 static int ar9003_hw_process_ini(struct ath_hw *ah, in ar9003_hw_process_ini() argument
798 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); in ar9003_hw_process_ini()
799 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); in ar9003_hw_process_ini()
800 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); in ar9003_hw_process_ini()
801 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); in ar9003_hw_process_ini()
802 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_process_ini()
803 ar9003_hw_prog_ini(ah, in ar9003_hw_process_ini()
804 &ah->ini_radio_post_sys2ant, in ar9003_hw_process_ini()
808 ar9003_doubler_fix(ah); in ar9003_hw_process_ini()
813 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); in ar9003_hw_process_ini()
815 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_process_ini()
819 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_process_ini()
820 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_process_ini()
822 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_process_ini()
829 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) || in ar9003_hw_process_ini()
830 (ar9003_hw_get_rx_gain_idx(ah) == 3)) { in ar9003_hw_process_ini()
831 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna, in ar9003_hw_process_ini()
836 if (AR_SREV_9550(ah)) in ar9003_hw_process_ini()
837 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, in ar9003_hw_process_ini()
843 if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { in ar9003_hw_process_ini()
846 if (AR_SREV_9550(ah)) in ar9003_hw_process_ini()
847 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
852 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, in ar9003_hw_process_ini()
855 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar9003_hw_process_ini()
862 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_process_ini()
863 REG_WRITE_ARRAY(&ah->iniModesFastClock, in ar9003_hw_process_ini()
869 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); in ar9003_hw_process_ini()
875 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_process_ini()
877 ah->modes_index = modesIndex; in ar9003_hw_process_ini()
878 ar9003_hw_override_ini(ah); in ar9003_hw_process_ini()
879 ar9003_hw_set_channel_regs(ah, chan); in ar9003_hw_process_ini()
880 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_process_ini()
881 ath9k_hw_apply_txpower(ah, chan, false); in ar9003_hw_process_ini()
886 static void ar9003_hw_set_rfmode(struct ath_hw *ah, in ar9003_hw_set_rfmode() argument
899 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_set_rfmode()
903 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, in ar9003_hw_set_rfmode()
906 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar9003_hw_set_rfmode()
909 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) in ar9003_hw_mark_phy_inactive() argument
911 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar9003_hw_mark_phy_inactive()
914 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, in ar9003_hw_set_delta_slope() argument
934 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_delta_slope()
937 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
940 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
942 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
951 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
955 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
957 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
961 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) in ar9003_hw_rfbus_req() argument
963 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar9003_hw_rfbus_req()
964 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar9003_hw_rfbus_req()
972 static void ar9003_hw_rfbus_done(struct ath_hw *ah) in ar9003_hw_rfbus_done() argument
974 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
976 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar9003_hw_rfbus_done()
978 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar9003_hw_rfbus_done()
981 static bool ar9003_hw_ani_control(struct ath_hw *ah, in ar9003_hw_ani_control() argument
984 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_control()
985 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_control()
986 struct ar5416AniState *aniState = &ah->ani; in ar9003_hw_ani_control()
994 switch (cmd & ah->ani_function) { in ar9003_hw_ani_control()
1005 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ar9003_hw_ani_control()
1029 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1032 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1035 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1038 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1041 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1044 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1047 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1050 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1053 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1056 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1061 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1064 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1075 ah->stats.ast_ani_ofdmon++; in ar9003_hw_ani_control()
1077 ah->stats.ast_ani_ofdmoff++; in ar9003_hw_ani_control()
1103 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar9003_hw_ani_control()
1119 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar9003_hw_ani_control()
1140 ah->stats.ast_ani_stepup++; in ar9003_hw_ani_control()
1142 ah->stats.ast_ani_stepdown++; in ar9003_hw_ani_control()
1167 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar9003_hw_ani_control()
1183 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar9003_hw_ani_control()
1204 ah->stats.ast_ani_spurup++; in ar9003_hw_ani_control()
1206 ah->stats.ast_ani_spurdown++; in ar9003_hw_ani_control()
1218 if (ah->caps.rx_chainmask == 1) in ar9003_hw_ani_control()
1221 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1223 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1231 ah->stats.ast_ani_ccklow++; in ar9003_hw_ani_control()
1233 ah->stats.ast_ani_cckhigh++; in ar9003_hw_ani_control()
1255 static void ar9003_hw_do_getnf(struct ath_hw *ah, in ar9003_hw_do_getnf() argument
1267 if (ah->rxchainmask & BIT(i)) { in ar9003_hw_do_getnf()
1268 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1272 if (IS_CHAN_HT40(ah->curchan)) { in ar9003_hw_do_getnf()
1275 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1283 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) in ar9003_hw_set_nf_limits() argument
1285 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1286 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1287 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1288 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1289 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1290 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1292 if (AR_SREV_9330(ah)) in ar9003_hw_set_nf_limits()
1293 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; in ar9003_hw_set_nf_limits()
1295 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_nf_limits()
1296 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1297 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1298 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1299 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1308 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar9003_hw_ani_cache_ini_regs() argument
1311 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_cache_ini_regs()
1312 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_cache_ini_regs()
1316 aniState = &ah->ani; in ar9003_hw_ani_cache_ini_regs()
1320 ah->hw_version.macVersion, in ar9003_hw_ani_cache_ini_regs()
1321 ah->hw_version.macRev, in ar9003_hw_ani_cache_ini_regs()
1322 ah->opmode, in ar9003_hw_ani_cache_ini_regs()
1325 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1330 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
1335 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar9003_hw_ani_cache_ini_regs()
1340 iniDef->firstep = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1343 iniDef->firstepLow = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1346 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1349 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1360 static void ar9003_hw_set_radar_params(struct ath_hw *ah, in ar9003_hw_set_radar_params() argument
1367 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar9003_hw_set_radar_params()
1384 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar9003_hw_set_radar_params()
1385 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar9003_hw_set_radar_params()
1387 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1389 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1391 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { in ar9003_hw_set_radar_params()
1392 REG_WRITE_ARRAY(&ah->ini_dfs, in ar9003_hw_set_radar_params()
1393 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); in ar9003_hw_set_radar_params()
1397 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) in ar9003_hw_set_radar_conf() argument
1399 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar9003_hw_set_radar_conf()
1411 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_get() argument
1416 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_get()
1424 if (AR_SREV_9330_11(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1428 } else if (AR_SREV_9485(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1432 } else if (AR_SREV_9565(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1443 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_set() argument
1448 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_set()
1465 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_antdiv_comb_conf_set()
1470 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) in ar9003_hw_set_bt_ant_diversity() argument
1472 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_set_bt_ant_diversity()
1476 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah)) in ar9003_hw_set_bt_ant_diversity()
1479 if (AR_SREV_9485(ah)) { in ar9003_hw_set_bt_ant_diversity()
1480 regval = ar9003_hw_ant_ctrl_common_2_get(ah, in ar9003_hw_set_bt_ant_diversity()
1481 IS_CHAN_2GHZ(ah->curchan)); in ar9003_hw_set_bt_ant_diversity()
1484 regval |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_set_bt_ant_diversity()
1486 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, in ar9003_hw_set_bt_ant_diversity()
1490 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_set_bt_ant_diversity()
1496 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1499 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1501 if (AR_SREV_9485_11_OR_LATER(ah)) { in ar9003_hw_set_bt_ant_diversity()
1505 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1511 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1516 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9003_hw_set_bt_ant_diversity()
1522 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9003_hw_set_bt_ant_diversity()
1525 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1538 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1540 } else if (AR_SREV_9565(ah)) { in ar9003_hw_set_bt_ant_diversity()
1542 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1544 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1546 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1548 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1550 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1553 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1555 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1557 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1559 REG_CLR_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1561 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1564 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1573 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1580 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, in ar9003_hw_fast_chan_change() argument
1592 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex; in ar9003_hw_fast_chan_change()
1594 if (modesIndex == ah->modes_index) { in ar9003_hw_fast_chan_change()
1599 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1600 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1601 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1602 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1604 if (AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_fast_chan_change()
1605 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, in ar9003_hw_fast_chan_change()
1608 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); in ar9003_hw_fast_chan_change()
1610 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_fast_chan_change()
1614 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_fast_chan_change()
1615 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_fast_chan_change()
1617 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_fast_chan_change()
1626 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_fast_chan_change()
1627 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); in ar9003_hw_fast_chan_change()
1629 if (AR_SREV_9565(ah)) in ar9003_hw_fast_chan_change()
1630 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); in ar9003_hw_fast_chan_change()
1636 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_fast_chan_change()
1638 ah->modes_index = modesIndex; in ar9003_hw_fast_chan_change()
1642 ar9003_hw_set_rfmode(ah, chan); in ar9003_hw_fast_chan_change()
1646 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, in ar9003_hw_spectral_scan_config() argument
1652 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1657 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9003_hw_spectral_scan_config()
1658 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9003_hw_spectral_scan_config()
1671 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1674 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1677 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1679 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1681 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1687 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) in ar9003_hw_spectral_scan_trigger() argument
1690 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1694 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) in ar9003_hw_spectral_scan_wait() argument
1696 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_spectral_scan_wait()
1699 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_wait()
1707 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) in ar9003_hw_tx99_start() argument
1709 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); in ar9003_hw_tx99_start()
1710 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_start()
1711 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9003_hw_tx99_start()
1712 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9003_hw_tx99_start()
1713 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ in ar9003_hw_tx99_start()
1714 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); in ar9003_hw_tx99_start()
1715 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); in ar9003_hw_tx99_start()
1716 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); in ar9003_hw_tx99_start()
1717 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9003_hw_tx99_start()
1720 static void ar9003_hw_tx99_stop(struct ath_hw *ah) in ar9003_hw_tx99_stop() argument
1722 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); in ar9003_hw_tx99_stop()
1723 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_stop()
1726 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) in ar9003_hw_tx99_set_txpower() argument
1739 REG_WRITE(ah, 0xa458, 0); in ar9003_hw_tx99_set_txpower()
1741 REG_WRITE(ah, 0xa3c0, in ar9003_hw_tx99_set_txpower()
1746 REG_WRITE(ah, 0xa3c4, in ar9003_hw_tx99_set_txpower()
1751 REG_WRITE(ah, 0xa3c8, in ar9003_hw_tx99_set_txpower()
1755 REG_WRITE(ah, 0xa3cc, in ar9003_hw_tx99_set_txpower()
1760 REG_WRITE(ah, 0xa3d0, in ar9003_hw_tx99_set_txpower()
1765 REG_WRITE(ah, 0xa3d4, in ar9003_hw_tx99_set_txpower()
1770 REG_WRITE(ah, 0xa3e4, in ar9003_hw_tx99_set_txpower()
1775 REG_WRITE(ah, 0xa3e8, in ar9003_hw_tx99_set_txpower()
1780 REG_WRITE(ah, 0xa3d8, in ar9003_hw_tx99_set_txpower()
1785 REG_WRITE(ah, 0xa3dc, in ar9003_hw_tx99_set_txpower()
1790 REG_WRITE(ah, 0xa3ec, in ar9003_hw_tx99_set_txpower()
1797 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) in ar9003_hw_attach_phy_ops() argument
1799 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9003_hw_attach_phy_ops()
1800 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9003_hw_attach_phy_ops()
1813 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) in ar9003_hw_attach_phy_ops()
1845 ar9003_hw_set_nf_limits(ah); in ar9003_hw_attach_phy_ops()
1846 ar9003_hw_set_radar_conf(ah); in ar9003_hw_attach_phy_ops()
1847 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); in ar9003_hw_attach_phy_ops()
1875 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) in ar9003_hw_bb_watchdog_check() argument
1879 switch(ah->bb_watchdog_last_status) { in ar9003_hw_bb_watchdog_check()
1881 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
1884 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
1886 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
1889 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
1898 if (AR_SREV_9340(ah) || AR_SREV_9531(ah)) in ar9003_hw_bb_watchdog_check()
1912 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) in ar9003_hw_bb_watchdog_config() argument
1914 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_config()
1915 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; in ar9003_hw_bb_watchdog_config()
1920 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
1921 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & in ar9003_hw_bb_watchdog_config()
1926 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
1927 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & in ar9003_hw_bb_watchdog_config()
1936 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; in ar9003_hw_bb_watchdog_config()
1937 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
1955 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) in ar9003_hw_bb_watchdog_config()
1962 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
1971 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) in ar9003_hw_bb_watchdog_read() argument
1977 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); in ar9003_hw_bb_watchdog_read()
1983 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, in ar9003_hw_bb_watchdog_read()
1984 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); in ar9003_hw_bb_watchdog_read()
1987 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) in ar9003_hw_bb_watchdog_dbg_info() argument
1989 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_dbg_info()
1995 status = ah->bb_watchdog_last_status; in ar9003_hw_bb_watchdog_dbg_info()
2011 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), in ar9003_hw_bb_watchdog_dbg_info()
2012 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); in ar9003_hw_bb_watchdog_dbg_info()
2014 REG_READ(ah, AR_PHY_GEN_CTRL)); in ar9003_hw_bb_watchdog_dbg_info()
2026 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) in ar9003_hw_disable_phy_restart() argument
2036 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); in ar9003_hw_disable_phy_restart()
2038 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { in ar9003_hw_disable_phy_restart()
2039 ah->bb_hang_rx_ofdm = true; in ar9003_hw_disable_phy_restart()
2040 val = REG_READ(ah, AR_PHY_RESTART); in ar9003_hw_disable_phy_restart()
2042 REG_WRITE(ah, AR_PHY_RESTART, val); in ar9003_hw_disable_phy_restart()