Lines Matching refs:ah
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
38 static void ath9k_hw_set_clockrate(struct ath_hw *ah) in ath9k_hw_set_clockrate() argument
40 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_clockrate()
41 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) in ath9k_hw_set_clockrate()
51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
68 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) in ath9k_hw_mac_to_clks() argument
70 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_mac_to_clks()
75 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) in ath9k_hw_wait() argument
82 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
88 ath_dbg(ath9k_hw_common(ah), ANY, in ath9k_hw_wait()
90 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
96 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_synth_delay() argument
109 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, in ath9k_hw_write_array() argument
114 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_write_array()
116 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
120 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_write_array()
135 u16 ath9k_hw_computetxtime(struct ath_hw *ah, in ath9k_hw_computetxtime() argument
154 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
161 } else if (ah->curchan && in ath9k_hw_computetxtime()
162 IS_CHAN_HALF_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
178 ath_err(ath9k_hw_common(ah), in ath9k_hw_computetxtime()
188 void ath9k_hw_get_channel_centers(struct ath_hw *ah, in ath9k_hw_get_channel_centers() argument
221 static void ath9k_hw_read_revisions(struct ath_hw *ah) in ath9k_hw_read_revisions() argument
225 if (ah->get_mac_revision) in ath9k_hw_read_revisions()
226 ah->hw_version.macRev = ah->get_mac_revision(); in ath9k_hw_read_revisions()
228 switch (ah->hw_version.devid) { in ath9k_hw_read_revisions()
230 ah->hw_version.macVersion = AR_SREV_VERSION_9100; in ath9k_hw_read_revisions()
233 ah->hw_version.macVersion = AR_SREV_VERSION_9330; in ath9k_hw_read_revisions()
234 if (!ah->get_mac_revision) { in ath9k_hw_read_revisions()
235 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
240 ah->hw_version.macVersion = AR_SREV_VERSION_9340; in ath9k_hw_read_revisions()
243 ah->hw_version.macVersion = AR_SREV_VERSION_9550; in ath9k_hw_read_revisions()
246 ah->hw_version.macVersion = AR_SREV_VERSION_9531; in ath9k_hw_read_revisions()
250 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; in ath9k_hw_read_revisions()
253 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
254 ah->hw_version.macVersion = in ath9k_hw_read_revisions()
256 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
258 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_read_revisions()
259 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
261 ah->is_pciexpress = (val & in ath9k_hw_read_revisions()
264 if (!AR_SREV_9100(ah)) in ath9k_hw_read_revisions()
265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); in ath9k_hw_read_revisions()
267 ah->hw_version.macRev = val & AR_SREV_REVISION; in ath9k_hw_read_revisions()
269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) in ath9k_hw_read_revisions()
270 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
278 static void ath9k_hw_disablepcie(struct ath_hw *ah) in ath9k_hw_disablepcie() argument
280 if (!AR_SREV_5416(ah)) in ath9k_hw_disablepcie()
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
297 static bool ath9k_hw_chip_test(struct ath_hw *ah) in ath9k_hw_chip_test() argument
299 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_chip_test()
307 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_chip_test()
317 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
320 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
321 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
331 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
332 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
340 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
347 static void ath9k_hw_init_config(struct ath_hw *ah) in ath9k_hw_init_config() argument
349 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_config()
351 ah->config.dma_beacon_response_time = 1; in ath9k_hw_init_config()
352 ah->config.sw_beacon_response_time = 6; in ath9k_hw_init_config()
353 ah->config.cwm_ignore_extcca = 0; in ath9k_hw_init_config()
354 ah->config.analog_shiftreg = 1; in ath9k_hw_init_config()
356 ah->config.rx_intr_mitigation = true; in ath9k_hw_init_config()
358 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_config()
359 ah->config.rimt_last = 500; in ath9k_hw_init_config()
360 ah->config.rimt_first = 2000; in ath9k_hw_init_config()
362 ah->config.rimt_last = 250; in ath9k_hw_init_config()
363 ah->config.rimt_first = 700; in ath9k_hw_init_config()
383 ah->config.serialize_regmode = SER_REG_MODE_AUTO; in ath9k_hw_init_config()
385 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { in ath9k_hw_init_config()
386 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || in ath9k_hw_init_config()
387 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && in ath9k_hw_init_config()
388 !ah->is_pciexpress)) { in ath9k_hw_init_config()
389 ah->config.serialize_regmode = SER_REG_MODE_ON; in ath9k_hw_init_config()
391 ah->config.serialize_regmode = SER_REG_MODE_OFF; in ath9k_hw_init_config()
396 ah->config.serialize_regmode); in ath9k_hw_init_config()
398 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_config()
399 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; in ath9k_hw_init_config()
401 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; in ath9k_hw_init_config()
404 static void ath9k_hw_init_defaults(struct ath_hw *ah) in ath9k_hw_init_defaults() argument
406 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_init_defaults()
411 ah->hw_version.magic = AR5416_MAGIC; in ath9k_hw_init_defaults()
412 ah->hw_version.subvendorid = 0; in ath9k_hw_init_defaults()
414 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | in ath9k_hw_init_defaults()
416 if (AR_SREV_9100(ah)) in ath9k_hw_init_defaults()
417 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; in ath9k_hw_init_defaults()
419 ah->slottime = ATH9K_SLOT_TIME_9; in ath9k_hw_init_defaults()
420 ah->globaltxtimeout = (u32) -1; in ath9k_hw_init_defaults()
421 ah->power_mode = ATH9K_PM_UNDEFINED; in ath9k_hw_init_defaults()
422 ah->htc_reset_init = true; in ath9k_hw_init_defaults()
424 ah->ani_function = ATH9K_ANI_ALL; in ath9k_hw_init_defaults()
425 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_init_defaults()
426 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; in ath9k_hw_init_defaults()
428 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_defaults()
429 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
431 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
434 static int ath9k_hw_init_macaddr(struct ath_hw *ah) in ath9k_hw_init_macaddr() argument
436 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_macaddr()
444 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); in ath9k_hw_init_macaddr()
455 static int ath9k_hw_post_init(struct ath_hw *ah) in ath9k_hw_post_init() argument
457 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_post_init()
461 if (!ath9k_hw_chip_test(ah)) in ath9k_hw_post_init()
465 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
466 ecode = ar9002_hw_rf_claim(ah); in ath9k_hw_post_init()
471 ecode = ath9k_hw_eeprom_init(ah); in ath9k_hw_post_init()
475 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", in ath9k_hw_post_init()
476 ah->eep_ops->get_eeprom_ver(ah), in ath9k_hw_post_init()
477 ah->eep_ops->get_eeprom_rev(ah)); in ath9k_hw_post_init()
479 ath9k_hw_ani_init(ah); in ath9k_hw_post_init()
485 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
486 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_post_init()
488 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; in ath9k_hw_post_init()
489 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; in ath9k_hw_post_init()
496 static int ath9k_hw_attach_ops(struct ath_hw *ah) in ath9k_hw_attach_ops() argument
498 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_attach_ops()
499 return ar9002_hw_attach_ops(ah); in ath9k_hw_attach_ops()
501 ar9003_hw_attach_ops(ah); in ath9k_hw_attach_ops()
506 static int __ath9k_hw_init(struct ath_hw *ah) in __ath9k_hw_init() argument
508 struct ath_common *common = ath9k_hw_common(ah); in __ath9k_hw_init()
511 ath9k_hw_read_revisions(ah); in __ath9k_hw_init()
513 switch (ah->hw_version.macVersion) { in __ath9k_hw_init()
534 ah->hw_version.macVersion, ah->hw_version.macRev); in __ath9k_hw_init()
543 if (AR_SREV_9300_20_OR_LATER(ah)) { in __ath9k_hw_init()
544 ah->WARegVal = REG_READ(ah, AR_WA); in __ath9k_hw_init()
545 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | in __ath9k_hw_init()
549 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in __ath9k_hw_init()
554 if (AR_SREV_9565(ah)) { in __ath9k_hw_init()
555 ah->WARegVal |= AR_WA_BIT22; in __ath9k_hw_init()
556 REG_WRITE(ah, AR_WA, ah->WARegVal); in __ath9k_hw_init()
559 ath9k_hw_init_defaults(ah); in __ath9k_hw_init()
560 ath9k_hw_init_config(ah); in __ath9k_hw_init()
562 r = ath9k_hw_attach_ops(ah); in __ath9k_hw_init()
566 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { in __ath9k_hw_init()
571 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || in __ath9k_hw_init()
572 AR_SREV_9330(ah) || AR_SREV_9550(ah)) in __ath9k_hw_init()
573 ah->is_pciexpress = false; in __ath9k_hw_init()
575 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
576 ath9k_hw_init_cal_settings(ah); in __ath9k_hw_init()
578 if (!ah->is_pciexpress) in __ath9k_hw_init()
579 ath9k_hw_disablepcie(ah); in __ath9k_hw_init()
581 r = ath9k_hw_post_init(ah); in __ath9k_hw_init()
585 ath9k_hw_init_mode_gain_regs(ah); in __ath9k_hw_init()
586 r = ath9k_hw_fill_cap_info(ah); in __ath9k_hw_init()
590 r = ath9k_hw_init_macaddr(ah); in __ath9k_hw_init()
596 ath9k_hw_init_hang_checks(ah); in __ath9k_hw_init()
603 int ath9k_hw_init(struct ath_hw *ah) in ath9k_hw_init() argument
606 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init()
609 switch (ah->hw_version.devid) { in ath9k_hw_init()
635 ah->hw_version.devid); in ath9k_hw_init()
639 ret = __ath9k_hw_init(ah); in ath9k_hw_init()
647 ath_dynack_init(ah); in ath9k_hw_init()
653 static void ath9k_hw_init_qos(struct ath_hw *ah) in ath9k_hw_init_qos() argument
655 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_qos()
657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
660 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
671 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_qos()
674 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) in ar9003_get_pll_sqsum_dvc() argument
676 struct ath_common *common = ath9k_hw_common(ah); in ar9003_get_pll_sqsum_dvc()
679 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
681 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
683 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
695 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; in ar9003_get_pll_sqsum_dvc()
699 static void ath9k_hw_init_pll(struct ath_hw *ah, in ath9k_hw_init_pll() argument
704 pll = ath9k_hw_compute_pll_control(ah, chan); in ath9k_hw_init_pll()
706 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_init_pll()
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
736 } else if (AR_SREV_9330(ah)) { in ath9k_hw_init_pll()
739 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
750 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); in ath9k_hw_init_pll()
753 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, in ath9k_hw_init_pll()
756 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
761 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); in ath9k_hw_init_pll()
764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); in ath9k_hw_init_pll()
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); in ath9k_hw_init_pll()
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
770 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { in ath9k_hw_init_pll()
773 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
777 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
780 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
781 if (AR_SREV_9531(ah)) { in ath9k_hw_init_pll()
791 if (AR_SREV_9340(ah)) { in ath9k_hw_init_pll()
798 AR_SREV_9531(ah) ? 0x26665 : 0x26666; in ath9k_hw_init_pll()
803 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
804 if (AR_SREV_9531(ah)) in ath9k_hw_init_pll()
808 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
811 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
815 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
816 if (AR_SREV_9340(ah)) in ath9k_hw_init_pll()
822 else if (AR_SREV_9531(ah)) in ath9k_hw_init_pll()
835 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
837 if (AR_SREV_9531(ah)) in ath9k_hw_init_pll()
838 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
839 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); in ath9k_hw_init_pll()
841 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
842 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); in ath9k_hw_init_pll()
847 if (AR_SREV_9565(ah)) in ath9k_hw_init_pll()
849 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ath9k_hw_init_pll()
851 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ath9k_hw_init_pll()
852 AR_SREV_9550(ah)) in ath9k_hw_init_pll()
856 if (AR_SREV_9271(ah)) { in ath9k_hw_init_pll()
858 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
863 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
866 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, in ath9k_hw_init_interrupt_masks() argument
876 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) in ath9k_hw_init_interrupt_masks()
879 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
881 if (ah->config.rx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
887 if (ah->config.rx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
893 if (ah->config.tx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
898 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_interrupt_masks()
900 REG_WRITE(ah, AR_IMR, imr_reg); in ath9k_hw_init_interrupt_masks()
901 ah->imrs2_reg |= AR_IMR_S2_GTT; in ath9k_hw_init_interrupt_masks()
902 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
904 if (!AR_SREV_9100(ah)) { in ath9k_hw_init_interrupt_masks()
905 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
906 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); in ath9k_hw_init_interrupt_masks()
907 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
910 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_interrupt_masks()
912 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
913 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
914 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
915 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
916 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
920 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) in ath9k_hw_set_sifs_time() argument
922 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); in ath9k_hw_set_sifs_time()
924 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); in ath9k_hw_set_sifs_time()
927 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) in ath9k_hw_setslottime() argument
929 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_setslottime()
931 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); in ath9k_hw_setslottime()
934 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_ack_timeout() argument
936 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_ack_timeout()
938 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); in ath9k_hw_set_ack_timeout()
941 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_cts_timeout() argument
943 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_cts_timeout()
945 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); in ath9k_hw_set_cts_timeout()
948 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) in ath9k_hw_set_global_txtimeout() argument
951 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", in ath9k_hw_set_global_txtimeout()
953 ah->globaltxtimeout = (u32) -1; in ath9k_hw_set_global_txtimeout()
956 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); in ath9k_hw_set_global_txtimeout()
957 ah->globaltxtimeout = tu; in ath9k_hw_set_global_txtimeout()
962 void ath9k_hw_init_global_settings(struct ath_hw *ah) in ath9k_hw_init_global_settings() argument
964 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_global_settings()
965 const struct ath9k_channel *chan = ah->curchan; in ath9k_hw_init_global_settings()
972 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", in ath9k_hw_init_global_settings()
973 ah->misc_mode); in ath9k_hw_init_global_settings()
978 if (ah->misc_mode != 0) in ath9k_hw_init_global_settings()
979 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
981 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
996 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1006 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1013 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_init_global_settings()
1017 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ in ath9k_hw_init_global_settings()
1019 reg = REG_READ(ah, AR_USEC); in ath9k_hw_init_global_settings()
1024 slottime = ah->slottime; in ath9k_hw_init_global_settings()
1028 slottime += 3 * ah->coverage_class; in ath9k_hw_init_global_settings()
1041 acktimeout += 64 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1042 ctstimeout += 48 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1045 if (ah->dynack.enabled) { in ath9k_hw_init_global_settings()
1046 acktimeout = ah->dynack.ackto; in ath9k_hw_init_global_settings()
1050 ah->dynack.ackto = acktimeout; in ath9k_hw_init_global_settings()
1053 ath9k_hw_set_sifs_time(ah, sifstime); in ath9k_hw_init_global_settings()
1054 ath9k_hw_setslottime(ah, slottime); in ath9k_hw_init_global_settings()
1055 ath9k_hw_set_ack_timeout(ah, acktimeout); in ath9k_hw_init_global_settings()
1056 ath9k_hw_set_cts_timeout(ah, ctstimeout); in ath9k_hw_init_global_settings()
1057 if (ah->globaltxtimeout != (u32) -1) in ath9k_hw_init_global_settings()
1058 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); in ath9k_hw_init_global_settings()
1060 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); in ath9k_hw_init_global_settings()
1061 REG_RMW(ah, AR_USEC, in ath9k_hw_init_global_settings()
1070 void ath9k_hw_deinit(struct ath_hw *ah) in ath9k_hw_deinit() argument
1072 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_deinit()
1077 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); in ath9k_hw_deinit()
1101 static inline void ath9k_hw_set_dma(struct ath_hw *ah) in ath9k_hw_set_dma() argument
1103 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_dma()
1106 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1111 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1112 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1117 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1119 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1126 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1127 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); in ath9k_hw_set_dma()
1129 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1134 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1139 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1141 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_dma()
1142 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); in ath9k_hw_set_dma()
1143 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); in ath9k_hw_set_dma()
1145 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - in ath9k_hw_set_dma()
1146 ah->caps.rx_status_len); in ath9k_hw_set_dma()
1153 if (AR_SREV_9285(ah)) { in ath9k_hw_set_dma()
1159 } else if (AR_SREV_9340_13_OR_LATER(ah)) { in ath9k_hw_set_dma()
1166 if (!AR_SREV_9271(ah)) in ath9k_hw_set_dma()
1167 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); in ath9k_hw_set_dma()
1169 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1171 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1172 ath9k_hw_reset_txstatus_ring(ah); in ath9k_hw_set_dma()
1175 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) in ath9k_hw_set_operating_mode() argument
1182 if (!AR_SREV_9340_13(ah)) { in ath9k_hw_set_operating_mode()
1184 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1193 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1196 if (!ah->is_monitoring) in ath9k_hw_set_operating_mode()
1200 REG_RMW(ah, AR_STA_ID1, set, mask); in ath9k_hw_set_operating_mode()
1203 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, in ath9k_hw_get_delta_slope_vals() argument
1225 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) in ath9k_hw_ar9330_reset_war() argument
1230 npend = ath9k_hw_numtxpending(ah, i); in ath9k_hw_ar9330_reset_war()
1235 if (ah->external_reset && in ath9k_hw_ar9330_reset_war()
1239 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_ar9330_reset_war()
1242 reset_err = ah->external_reset(); in ath9k_hw_ar9330_reset_war()
1244 ath_err(ath9k_hw_common(ah), in ath9k_hw_ar9330_reset_war()
1250 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_ar9330_reset_war()
1256 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) in ath9k_hw_set_reset() argument
1261 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1262 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, in ath9k_hw_set_reset()
1264 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); in ath9k_hw_set_reset()
1267 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset()
1269 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset()
1270 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset()
1274 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1277 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1281 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); in ath9k_hw_set_reset()
1282 if (AR_SREV_9340(ah)) in ath9k_hw_set_reset()
1290 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_reset()
1293 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1295 REG_WRITE(ah, AR_RC, val); in ath9k_hw_set_reset()
1297 } else if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1298 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1305 if (AR_SREV_9330(ah)) { in ath9k_hw_set_reset()
1306 if (!ath9k_hw_ar9330_reset_war(ah, type)) in ath9k_hw_set_reset()
1310 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_reset()
1311 ar9003_mci_check_gpm_offset(ah); in ath9k_hw_set_reset()
1313 REG_WRITE(ah, AR_RTC_RC, rst_flags); in ath9k_hw_set_reset()
1315 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset()
1317 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1319 else if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1324 REG_WRITE(ah, AR_RTC_RC, 0); in ath9k_hw_set_reset()
1325 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_reset()
1326 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); in ath9k_hw_set_reset()
1330 if (!AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1331 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1333 if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1339 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) in ath9k_hw_set_reset_power_on() argument
1341 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset_power_on()
1343 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_power_on()
1344 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_power_on()
1348 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1351 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1352 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset_power_on()
1354 REG_WRITE(ah, AR_RTC_RESET, 0); in ath9k_hw_set_reset_power_on()
1356 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset_power_on()
1360 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1361 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1363 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_set_reset_power_on()
1365 if (!ath9k_hw_wait(ah, in ath9k_hw_set_reset_power_on()
1370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); in ath9k_hw_set_reset_power_on()
1374 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); in ath9k_hw_set_reset_power_on()
1377 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) in ath9k_hw_set_reset_reg() argument
1381 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_reg()
1382 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_reg()
1386 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_reset_reg()
1389 if (!ah->reset_power_on) in ath9k_hw_set_reset_reg()
1394 ret = ath9k_hw_set_reset_power_on(ah); in ath9k_hw_set_reset_reg()
1396 ah->reset_power_on = true; in ath9k_hw_set_reset_reg()
1400 ret = ath9k_hw_set_reset(ah, type); in ath9k_hw_set_reset_reg()
1409 static bool ath9k_hw_chip_reset(struct ath_hw *ah, in ath9k_hw_chip_reset() argument
1414 if (AR_SREV_9280(ah)) { in ath9k_hw_chip_reset()
1415 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) in ath9k_hw_chip_reset()
1419 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || in ath9k_hw_chip_reset()
1420 (REG_READ(ah, AR_CR) & AR_CR_RXE)) in ath9k_hw_chip_reset()
1423 if (!ath9k_hw_set_reset_reg(ah, reset_type)) in ath9k_hw_chip_reset()
1426 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_chip_reset()
1429 ah->chip_fullsleep = false; in ath9k_hw_chip_reset()
1431 if (AR_SREV_9330(ah)) in ath9k_hw_chip_reset()
1432 ar9003_hw_internal_regulator_apply(ah); in ath9k_hw_chip_reset()
1433 ath9k_hw_init_pll(ah, chan); in ath9k_hw_chip_reset()
1438 static bool ath9k_hw_channel_change(struct ath_hw *ah, in ath9k_hw_channel_change() argument
1441 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_channel_change()
1442 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_channel_change()
1449 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; in ath9k_hw_channel_change()
1455 if (ath9k_hw_numtxpending(ah, qnum)) { in ath9k_hw_channel_change()
1462 if (!ath9k_hw_rfbus_req(ah)) { in ath9k_hw_channel_change()
1468 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_channel_change()
1472 ath9k_hw_init_pll(ah, chan); in ath9k_hw_channel_change()
1474 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { in ath9k_hw_channel_change()
1480 ath9k_hw_set_channel_regs(ah, chan); in ath9k_hw_channel_change()
1482 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_channel_change()
1487 ath9k_hw_set_clockrate(ah); in ath9k_hw_channel_change()
1488 ath9k_hw_apply_txpower(ah, chan, false); in ath9k_hw_channel_change()
1490 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_channel_change()
1491 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_channel_change()
1494 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_channel_change()
1496 ath9k_hw_init_bb(ah, chan); in ath9k_hw_channel_change()
1497 ath9k_hw_rfbus_done(ah); in ath9k_hw_channel_change()
1500 ah->ah_flags |= AH_FASTCC; in ath9k_hw_channel_change()
1501 ath9k_hw_init_cal(ah, chan); in ath9k_hw_channel_change()
1502 ah->ah_flags &= ~AH_FASTCC; in ath9k_hw_channel_change()
1508 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) in ath9k_hw_apply_gpio_override() argument
1510 u32 gpio_mask = ah->gpio_mask; in ath9k_hw_apply_gpio_override()
1517 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); in ath9k_hw_apply_gpio_override()
1518 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); in ath9k_hw_apply_gpio_override()
1522 void ath9k_hw_check_nav(struct ath_hw *ah) in ath9k_hw_check_nav() argument
1524 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_check_nav()
1527 val = REG_READ(ah, AR_NAV); in ath9k_hw_check_nav()
1530 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1535 bool ath9k_hw_check_alive(struct ath_hw *ah) in ath9k_hw_check_alive() argument
1540 if (AR_SREV_9300(ah)) in ath9k_hw_check_alive()
1541 return !ath9k_hw_detect_mac_hang(ah); in ath9k_hw_check_alive()
1543 if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_check_alive()
1546 last_val = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1548 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1571 static void ath9k_hw_init_mfp(struct ath_hw *ah) in ath9k_hw_init_mfp() argument
1574 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1577 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, in ath9k_hw_init_mfp()
1579 ah->sw_mgmt_crypto = false; in ath9k_hw_init_mfp()
1580 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1582 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1584 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1586 ah->sw_mgmt_crypto = true; in ath9k_hw_init_mfp()
1588 ah->sw_mgmt_crypto = true; in ath9k_hw_init_mfp()
1592 static void ath9k_hw_reset_opmode(struct ath_hw *ah, in ath9k_hw_reset_opmode() argument
1595 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset_opmode()
1597 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset_opmode()
1599 REG_RMW(ah, AR_STA_ID1, macStaId1 in ath9k_hw_reset_opmode()
1601 | ah->sta_id1_defaults, in ath9k_hw_reset_opmode()
1604 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset_opmode()
1605 ath9k_hw_write_associd(ah); in ath9k_hw_reset_opmode()
1606 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1607 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset_opmode()
1609 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset_opmode()
1611 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_reset_opmode()
1614 static void ath9k_hw_init_queues(struct ath_hw *ah) in ath9k_hw_init_queues() argument
1618 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_queues()
1621 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_init_queues()
1623 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_queues()
1625 ah->intr_txqs = 0; in ath9k_hw_init_queues()
1627 ath9k_hw_resettxqueue(ah, i); in ath9k_hw_init_queues()
1633 static void ath9k_hw_init_desc(struct ath_hw *ah) in ath9k_hw_init_desc() argument
1635 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_desc()
1637 if (AR_SREV_9100(ah)) { in ath9k_hw_init_desc()
1639 mask = REG_READ(ah, AR_CFG); in ath9k_hw_init_desc()
1645 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_init_desc()
1647 REG_READ(ah, AR_CFG)); in ath9k_hw_init_desc()
1652 if (AR_SREV_9271(ah)) in ath9k_hw_init_desc()
1653 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_init_desc()
1655 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1658 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || in ath9k_hw_init_desc()
1659 AR_SREV_9550(ah) || AR_SREV_9531(ah)) in ath9k_hw_init_desc()
1660 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); in ath9k_hw_init_desc()
1662 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1671 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_do_fastcc() argument
1673 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_do_fastcc()
1674 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_do_fastcc()
1677 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) in ath9k_hw_do_fastcc()
1680 if (ah->chip_fullsleep) in ath9k_hw_do_fastcc()
1683 if (!ah->curchan) in ath9k_hw_do_fastcc()
1686 if (chan->channel == ah->curchan->channel) in ath9k_hw_do_fastcc()
1689 if ((ah->curchan->channelFlags | chan->channelFlags) & in ath9k_hw_do_fastcc()
1697 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) in ath9k_hw_do_fastcc()
1700 if (!ath9k_hw_check_alive(ah)) in ath9k_hw_do_fastcc()
1707 if (AR_SREV_9462(ah) && (ah->caldata && in ath9k_hw_do_fastcc()
1708 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1709 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1710 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) in ath9k_hw_do_fastcc()
1714 ah->curchan->channel, chan->channel); in ath9k_hw_do_fastcc()
1716 ret = ath9k_hw_channel_change(ah, chan); in ath9k_hw_do_fastcc()
1720 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_do_fastcc()
1721 ar9003_mci_2g5g_switch(ah, false); in ath9k_hw_do_fastcc()
1723 ath9k_hw_loadnf(ah, ah->curchan); in ath9k_hw_do_fastcc()
1724 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_do_fastcc()
1726 if (AR_SREV_9271(ah)) in ath9k_hw_do_fastcc()
1727 ar9002_hw_load_ani_reg(ah, chan); in ath9k_hw_do_fastcc()
1751 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_reset() argument
1754 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset()
1762 bool save_fullsleep = ah->chip_fullsleep; in ath9k_hw_reset()
1764 if (ath9k_hw_mci_is_enabled(ah)) { in ath9k_hw_reset()
1765 start_mci_reset = ar9003_mci_start_reset(ah, chan); in ath9k_hw_reset()
1770 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_reset()
1773 if (ah->curchan && !ah->chip_fullsleep) in ath9k_hw_reset()
1774 ath9k_hw_getnf(ah, ah->curchan); in ath9k_hw_reset()
1776 ah->caldata = caldata; in ath9k_hw_reset()
1781 ath9k_init_nfcal_hist_buffer(ah, chan); in ath9k_hw_reset()
1785 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); in ath9k_hw_reset()
1788 r = ath9k_hw_do_fastcc(ah, chan); in ath9k_hw_reset()
1793 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1794 ar9003_mci_stop_bt(ah, save_fullsleep); in ath9k_hw_reset()
1796 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); in ath9k_hw_reset()
1800 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; in ath9k_hw_reset()
1803 tsf = ath9k_hw_gettsf64(ah); in ath9k_hw_reset()
1806 saveLedState = REG_READ(ah, AR_CFG_LED) & in ath9k_hw_reset()
1810 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_reset()
1812 ah->paprd_table_write_done = false; in ath9k_hw_reset()
1815 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1816 REG_WRITE(ah, in ath9k_hw_reset()
1822 if (!ath9k_hw_chip_reset(ah, chan)) { in ath9k_hw_reset()
1828 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1829 ah->htc_reset_init = false; in ath9k_hw_reset()
1830 REG_WRITE(ah, in ath9k_hw_reset()
1838 ath9k_hw_settsf64(ah, tsf + usec); in ath9k_hw_reset()
1840 if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_reset()
1841 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1843 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
1844 ar9002_hw_enable_async_fifo(ah); in ath9k_hw_reset()
1846 r = ath9k_hw_process_ini(ah, chan); in ath9k_hw_reset()
1850 ath9k_hw_set_rfmode(ah, chan); in ath9k_hw_reset()
1852 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1853 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); in ath9k_hw_reset()
1861 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { in ath9k_hw_reset()
1863 ath9k_hw_settsf64(ah, tsf); in ath9k_hw_reset()
1866 ath9k_hw_init_mfp(ah); in ath9k_hw_reset()
1868 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_reset()
1869 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_reset()
1870 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_reset()
1872 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); in ath9k_hw_reset()
1874 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_reset()
1878 ath9k_hw_set_clockrate(ah); in ath9k_hw_reset()
1880 ath9k_hw_init_queues(ah); in ath9k_hw_reset()
1881 ath9k_hw_init_interrupt_masks(ah, ah->opmode); in ath9k_hw_reset()
1882 ath9k_hw_ani_cache_ini_regs(ah); in ath9k_hw_reset()
1883 ath9k_hw_init_qos(ah); in ath9k_hw_reset()
1885 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
1886 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); in ath9k_hw_reset()
1888 ath9k_hw_init_global_settings(ah); in ath9k_hw_reset()
1890 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_reset()
1891 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ath9k_hw_reset()
1893 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, in ath9k_hw_reset()
1895 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
1899 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
1901 ath9k_hw_set_dma(ah); in ath9k_hw_reset()
1903 if (!ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1904 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
1906 if (ah->config.rx_intr_mitigation) { in ath9k_hw_reset()
1907 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); in ath9k_hw_reset()
1908 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); in ath9k_hw_reset()
1911 if (ah->config.tx_intr_mitigation) { in ath9k_hw_reset()
1912 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); in ath9k_hw_reset()
1913 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); in ath9k_hw_reset()
1916 ath9k_hw_init_bb(ah, chan); in ath9k_hw_reset()
1922 if (!ath9k_hw_init_cal(ah, chan)) in ath9k_hw_reset()
1925 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) in ath9k_hw_reset()
1928 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset()
1930 ath9k_hw_restore_chainmask(ah); in ath9k_hw_reset()
1931 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
1933 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset()
1935 ath9k_hw_init_desc(ah); in ath9k_hw_reset()
1937 if (ath9k_hw_btcoex_is_enabled(ah)) in ath9k_hw_reset()
1938 ath9k_hw_btcoex_enable(ah); in ath9k_hw_reset()
1940 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1941 ar9003_mci_check_bt(ah); in ath9k_hw_reset()
1943 ath9k_hw_loadnf(ah, chan); in ath9k_hw_reset()
1944 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_reset()
1946 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
1947 ar9003_hw_bb_watchdog_config(ah); in ath9k_hw_reset()
1949 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) in ath9k_hw_reset()
1950 ar9003_hw_disable_phy_restart(ah); in ath9k_hw_reset()
1952 ath9k_hw_apply_gpio_override(ah); in ath9k_hw_reset()
1954 if (AR_SREV_9565(ah) && common->bt_ant_diversity) in ath9k_hw_reset()
1955 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); in ath9k_hw_reset()
1957 if (ah->hw->conf.radar_enabled) { in ath9k_hw_reset()
1959 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); in ath9k_hw_reset()
1960 ath9k_hw_set_radar_params(ah); in ath9k_hw_reset()
1975 static void ath9k_set_power_sleep(struct ath_hw *ah) in ath9k_set_power_sleep() argument
1977 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_sleep()
1979 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_set_power_sleep()
1980 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
1981 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
1982 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
1984 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
1992 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep()
1994 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_sleep()
1997 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
1998 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
2001 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { in ath9k_set_power_sleep()
2002 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); in ath9k_set_power_sleep()
2007 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2008 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
2016 static void ath9k_set_power_network_sleep(struct ath_hw *ah) in ath9k_set_power_network_sleep() argument
2018 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_set_power_network_sleep()
2020 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_network_sleep()
2024 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2037 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2038 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep()
2044 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_network_sleep()
2046 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2051 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_network_sleep()
2052 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
2055 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) in ath9k_hw_set_power_awake() argument
2061 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_power_awake()
2062 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_power_awake()
2066 if ((REG_READ(ah, AR_RTC_STATUS) & in ath9k_hw_set_power_awake()
2068 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in ath9k_hw_set_power_awake()
2071 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_power_awake()
2072 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_set_power_awake()
2074 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2075 REG_SET_BIT(ah, AR_RTC_RESET, in ath9k_hw_set_power_awake()
2078 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2080 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2086 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; in ath9k_hw_set_power_awake()
2090 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2094 ath_err(ath9k_hw_common(ah), in ath9k_hw_set_power_awake()
2100 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_power_awake()
2101 ar9003_mci_set_power_awake(ah); in ath9k_hw_set_power_awake()
2103 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
2108 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) in ath9k_hw_setpower() argument
2110 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_setpower()
2119 if (ah->power_mode == mode) in ath9k_hw_setpower()
2123 modes[ah->power_mode], modes[mode]); in ath9k_hw_setpower()
2127 status = ath9k_hw_set_power_awake(ah); in ath9k_hw_setpower()
2130 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_setpower()
2131 ar9003_mci_set_full_sleep(ah); in ath9k_hw_setpower()
2133 ath9k_set_power_sleep(ah); in ath9k_hw_setpower()
2134 ah->chip_fullsleep = true; in ath9k_hw_setpower()
2137 ath9k_set_power_network_sleep(ah); in ath9k_hw_setpower()
2143 ah->power_mode = mode; in ath9k_hw_setpower()
2151 if (!(ah->ah_flags & AH_UNPLUGGED)) in ath9k_hw_setpower()
2162 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) in ath9k_hw_beaconinit() argument
2166 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_beaconinit()
2168 switch (ah->opmode) { in ath9k_hw_beaconinit()
2170 REG_SET_BIT(ah, AR_TXCFG, in ath9k_hw_beaconinit()
2174 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); in ath9k_hw_beaconinit()
2175 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2176 TU_TO_USEC(ah->config.dma_beacon_response_time)); in ath9k_hw_beaconinit()
2177 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2178 TU_TO_USEC(ah->config.sw_beacon_response_time)); in ath9k_hw_beaconinit()
2183 ath_dbg(ath9k_hw_common(ah), BEACON, in ath9k_hw_beaconinit()
2184 "%s: unsupported opmode: %d\n", __func__, ah->opmode); in ath9k_hw_beaconinit()
2189 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2190 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2191 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2193 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_beaconinit()
2195 REG_SET_BIT(ah, AR_TIMER_MODE, flags); in ath9k_hw_beaconinit()
2199 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, in ath9k_hw_set_sta_beacon_timers() argument
2203 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_set_sta_beacon_timers()
2204 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_sta_beacon_timers()
2206 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2208 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); in ath9k_hw_set_sta_beacon_timers()
2209 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2210 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2212 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2214 REG_RMW_FIELD(ah, AR_RSSI_THR, in ath9k_hw_set_sta_beacon_timers()
2236 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2238 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2239 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2241 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2250 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
2253 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); in ath9k_hw_set_sta_beacon_timers()
2254 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); in ath9k_hw_set_sta_beacon_timers()
2256 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2258 REG_SET_BIT(ah, AR_TIMER_MODE, in ath9k_hw_set_sta_beacon_timers()
2263 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2293 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) in ath9k_hw_dfs_tested() argument
2296 switch (ah->hw_version.macVersion) { in ath9k_hw_dfs_tested()
2307 int ath9k_hw_fill_cap_info(struct ath_hw *ah) in ath9k_hw_fill_cap_info() argument
2309 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_fill_cap_info()
2310 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_fill_cap_info()
2311 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_fill_cap_info()
2317 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_fill_cap_info()
2320 if (ah->opmode != NL80211_IFTYPE_AP && in ath9k_hw_fill_cap_info()
2321 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { in ath9k_hw_fill_cap_info()
2331 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); in ath9k_hw_fill_cap_info()
2344 if (AR_SREV_9485(ah) || in ath9k_hw_fill_cap_info()
2345 AR_SREV_9285(ah) || in ath9k_hw_fill_cap_info()
2346 AR_SREV_9330(ah) || in ath9k_hw_fill_cap_info()
2347 AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2349 else if (AR_SREV_9462(ah)) in ath9k_hw_fill_cap_info()
2351 else if (!AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2353 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) in ath9k_hw_fill_cap_info()
2358 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); in ath9k_hw_fill_cap_info()
2363 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && in ath9k_hw_fill_cap_info()
2365 !(AR_SREV_9271(ah))) in ath9k_hw_fill_cap_info()
2367 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; in ath9k_hw_fill_cap_info()
2368 else if (AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2372 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); in ath9k_hw_fill_cap_info()
2376 ah->txchainmask = pCap->tx_chainmask; in ath9k_hw_fill_cap_info()
2377 ah->rxchainmask = pCap->rx_chainmask; in ath9k_hw_fill_cap_info()
2379 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; in ath9k_hw_fill_cap_info()
2382 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2383 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; in ath9k_hw_fill_cap_info()
2387 if (ah->hw_version.devid != AR2427_DEVID_PCIE) in ath9k_hw_fill_cap_info()
2392 if (AR_SREV_9271(ah)) in ath9k_hw_fill_cap_info()
2394 else if (AR_DEVID_7010(ah)) in ath9k_hw_fill_cap_info()
2396 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2398 else if (AR_SREV_9287_11_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2400 else if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2402 else if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2407 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2413 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); in ath9k_hw_fill_cap_info()
2414 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { in ath9k_hw_fill_cap_info()
2415 ah->rfkill_gpio = in ath9k_hw_fill_cap_info()
2416 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); in ath9k_hw_fill_cap_info()
2417 ah->rfkill_polarity = in ath9k_hw_fill_cap_info()
2418 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); in ath9k_hw_fill_cap_info()
2423 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2428 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) in ath9k_hw_fill_cap_info()
2433 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2435 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2445 if (AR_SREV_9280_20(ah)) in ath9k_hw_fill_cap_info()
2449 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2452 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2453 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); in ath9k_hw_fill_cap_info()
2455 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) in ath9k_hw_fill_cap_info()
2458 if (AR_SREV_9285(ah)) { in ath9k_hw_fill_cap_info()
2459 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { in ath9k_hw_fill_cap_info()
2461 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2469 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2470 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) in ath9k_hw_fill_cap_info()
2474 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2475 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2482 if (ath9k_hw_dfs_tested(ah)) in ath9k_hw_fill_cap_info()
2497 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2498 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) in ath9k_hw_fill_cap_info()
2501 if (AR_SREV_9462_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2505 if (AR_SREV_9462(ah)) in ath9k_hw_fill_cap_info()
2508 if (AR_SREV_9300_20_OR_LATER(ah) && in ath9k_hw_fill_cap_info()
2509 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) in ath9k_hw_fill_cap_info()
2519 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, in ath9k_hw_gpio_cfg_output_mux() argument
2534 if (AR_SREV_9280_20_OR_LATER(ah) in ath9k_hw_gpio_cfg_output_mux()
2536 REG_RMW(ah, addr, (type << gpio_shift), in ath9k_hw_gpio_cfg_output_mux()
2539 tmp = REG_READ(ah, addr); in ath9k_hw_gpio_cfg_output_mux()
2543 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
2547 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) in ath9k_hw_cfg_gpio_input() argument
2551 BUG_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_cfg_gpio_input()
2553 if (AR_DEVID_7010(ah)) { in ath9k_hw_cfg_gpio_input()
2555 REG_RMW(ah, AR7010_GPIO_OE, in ath9k_hw_cfg_gpio_input()
2562 REG_RMW(ah, in ath9k_hw_cfg_gpio_input()
2569 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) in ath9k_hw_gpio_get() argument
2572 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) in ath9k_hw_gpio_get()
2574 if (gpio >= ah->caps.num_gpio_pins) in ath9k_hw_gpio_get()
2577 if (AR_DEVID_7010(ah)) { in ath9k_hw_gpio_get()
2579 val = REG_READ(ah, AR7010_GPIO_IN); in ath9k_hw_gpio_get()
2581 } else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_gpio_get()
2582 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & in ath9k_hw_gpio_get()
2584 else if (AR_SREV_9271(ah)) in ath9k_hw_gpio_get()
2586 else if (AR_SREV_9287_11_OR_LATER(ah)) in ath9k_hw_gpio_get()
2588 else if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_gpio_get()
2590 else if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_gpio_get()
2597 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, in ath9k_hw_cfg_output() argument
2602 if (AR_DEVID_7010(ah)) { in ath9k_hw_cfg_output()
2604 REG_RMW(ah, AR7010_GPIO_OE, in ath9k_hw_cfg_output()
2610 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); in ath9k_hw_cfg_output()
2612 REG_RMW(ah, in ath9k_hw_cfg_output()
2619 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) in ath9k_hw_set_gpio() argument
2621 if (AR_DEVID_7010(ah)) { in ath9k_hw_set_gpio()
2623 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), in ath9k_hw_set_gpio()
2628 if (AR_SREV_9271(ah)) in ath9k_hw_set_gpio()
2631 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), in ath9k_hw_set_gpio()
2636 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) in ath9k_hw_setantenna() argument
2638 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2646 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) in ath9k_hw_getrxfilter() argument
2648 u32 bits = REG_READ(ah, AR_RX_FILTER); in ath9k_hw_getrxfilter()
2649 u32 phybits = REG_READ(ah, AR_PHY_ERR); in ath9k_hw_getrxfilter()
2660 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) in ath9k_hw_setrxfilter() argument
2664 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_setrxfilter()
2666 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_setrxfilter()
2669 REG_WRITE(ah, AR_RX_FILTER, bits); in ath9k_hw_setrxfilter()
2676 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
2679 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2681 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2683 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_setrxfilter()
2687 bool ath9k_hw_phy_disable(struct ath_hw *ah) in ath9k_hw_phy_disable() argument
2689 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_phy_disable()
2690 ar9003_mci_bt_gain_ctrl(ah); in ath9k_hw_phy_disable()
2692 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) in ath9k_hw_phy_disable()
2695 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_phy_disable()
2696 ah->htc_reset_init = true; in ath9k_hw_phy_disable()
2701 bool ath9k_hw_disable(struct ath_hw *ah) in ath9k_hw_disable() argument
2703 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_disable()
2706 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) in ath9k_hw_disable()
2709 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_disable()
2714 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) in get_antenna_gain() argument
2723 return ah->eep_ops->get_eeprom(ah, gain_param); in get_antenna_gain()
2726 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_apply_txpower() argument
2729 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_apply_txpower()
2742 ant_gain = get_antenna_gain(ah, chan); in ath9k_hw_apply_txpower()
2746 ah->eep_ops->set_txpower(ah, chan, in ath9k_hw_apply_txpower()
2751 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) in ath9k_hw_set_txpowerlimit() argument
2753 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_set_txpowerlimit()
2754 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_txpowerlimit()
2761 ath9k_hw_apply_txpower(ah, chan, test); in ath9k_hw_set_txpowerlimit()
2768 void ath9k_hw_setopmode(struct ath_hw *ah) in ath9k_hw_setopmode() argument
2770 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_setopmode()
2774 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) in ath9k_hw_setmcastfilter() argument
2776 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
2777 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
2781 void ath9k_hw_write_associd(struct ath_hw *ah) in ath9k_hw_write_associd() argument
2783 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_write_associd()
2785 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
2786 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
2793 u64 ath9k_hw_gettsf64(struct ath_hw *ah) in ath9k_hw_gettsf64() argument
2798 tsf_upper1 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
2800 tsf_lower = REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf64()
2801 tsf_upper2 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
2813 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) in ath9k_hw_settsf64() argument
2815 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
2816 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
2820 void ath9k_hw_reset_tsf(struct ath_hw *ah) in ath9k_hw_reset_tsf() argument
2822 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, in ath9k_hw_reset_tsf()
2824 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_reset_tsf()
2827 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
2831 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) in ath9k_hw_set_tsfadjust() argument
2834 ah->misc_mode |= AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
2836 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
2840 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_set11nmac2040() argument
2844 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) in ath9k_hw_set11nmac2040()
2849 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()
2883 u32 ath9k_hw_gettsf32(struct ath_hw *ah) in ath9k_hw_gettsf32() argument
2885 return REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf32()
2889 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, in ath_gen_timer_alloc() argument
2895 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_alloc()
2917 void ath9k_hw_gen_timer_start(struct ath_hw *ah, in ath9k_hw_gen_timer_start() argument
2922 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start()
2930 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
2932 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()
2934 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_start()
2937 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_start()
2944 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
2947 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
2958 REG_SET_BIT(ah, AR_IMR_S5, mask); in ath9k_hw_gen_timer_start()
2960 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { in ath9k_hw_gen_timer_start()
2961 ah->imask |= ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_start()
2962 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_start()
2967 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) in ath9k_hw_gen_timer_stop() argument
2969 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_stop()
2972 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop()
2975 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_stop()
2980 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_stop()
2986 REG_CLR_BIT(ah, AR_IMR_S5, in ath9k_hw_gen_timer_stop()
2993 ah->imask &= ~ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_stop()
2994 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_stop()
2999 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) in ath_gen_timer_free() argument
3001 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_free()
3012 void ath_gen_timer_isr(struct ath_hw *ah) in ath_gen_timer_isr() argument
3014 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_isr()
3020 trigger_mask = ah->intr_gen_timer_trigger; in ath_gen_timer_isr()
3021 thresh_mask = ah->intr_gen_timer_thresh; in ath_gen_timer_isr()
3120 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) in ath9k_hw_name() argument
3125 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_name()
3128 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3129 ah->hw_version.macRev); in ath9k_hw_name()
3134 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3135 ah->hw_version.macRev, in ath9k_hw_name()
3136 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev in ath9k_hw_name()
3138 ah->hw_version.phyRev); in ath9k_hw_name()