132 	else if (rfpath == RF90_PATH_B)  in _rtl92c_phy_rf_serial_read()
439 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl92c_phy_init_bb_rf_register_definition()
444 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl92c_phy_init_bb_rf_register_definition()
449 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in _rtl92c_phy_init_bb_rf_register_definition()
452 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in _rtl92c_phy_init_bb_rf_register_definition()
456 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in _rtl92c_phy_init_bb_rf_register_definition()
460 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;  in _rtl92c_phy_init_bb_rf_register_definition()
465 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92c_phy_init_bb_rf_register_definition()
470 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;  in _rtl92c_phy_init_bb_rf_register_definition()
473 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in _rtl92c_phy_init_bb_rf_register_definition()
476 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in _rtl92c_phy_init_bb_rf_register_definition()
481 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;  in _rtl92c_phy_init_bb_rf_register_definition()
486 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;  in _rtl92c_phy_init_bb_rf_register_definition()
491 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;  in _rtl92c_phy_init_bb_rf_register_definition()
496 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;  in _rtl92c_phy_init_bb_rf_register_definition()
501 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;  in _rtl92c_phy_init_bb_rf_register_definition()
506 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;  in _rtl92c_phy_init_bb_rf_register_definition()
511 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in _rtl92c_phy_init_bb_rf_register_definition()
516 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;  in _rtl92c_phy_init_bb_rf_register_definition()
558 	cckpowerlevel[RF90_PATH_B] =  in _rtl92c_get_txpower_index()
559 	    rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];  in _rtl92c_get_txpower_index()
563 		ofdmpowerlevel[RF90_PATH_B] =  in _rtl92c_get_txpower_index()
564 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];  in _rtl92c_get_txpower_index()
568 		ofdmpowerlevel[RF90_PATH_B] =  in _rtl92c_get_txpower_index()
569 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];  in _rtl92c_get_txpower_index()