123 	else if (rfpath == RF90_PATH_B)  in rtl8723_phy_rf_serial_read()
194 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in rtl8723_phy_init_bb_rf_reg_def()
199 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in rtl8723_phy_init_bb_rf_reg_def()
204 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in rtl8723_phy_init_bb_rf_reg_def()
207 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in rtl8723_phy_init_bb_rf_reg_def()
211 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in rtl8723_phy_init_bb_rf_reg_def()
215 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in rtl8723_phy_init_bb_rf_reg_def()
220 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in rtl8723_phy_init_bb_rf_reg_def()
225 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;  in rtl8723_phy_init_bb_rf_reg_def()
228 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in rtl8723_phy_init_bb_rf_reg_def()
231 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in rtl8723_phy_init_bb_rf_reg_def()
236 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;  in rtl8723_phy_init_bb_rf_reg_def()
241 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;  in rtl8723_phy_init_bb_rf_reg_def()
246 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
251 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
256 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
261 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
266 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in rtl8723_phy_init_bb_rf_reg_def()
271 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;  in rtl8723_phy_init_bb_rf_reg_def()