Lines Matching refs:mem_ptr
2058 (unsigned long)ha->mem_ptr); in ips_host_info()
2261 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2265 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_get_bios_version()
2268 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2272 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_get_bios_version()
2276 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2280 major = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2283 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2286 minor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2289 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2292 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
4271 if (ha->mem_ptr) { in ips_free()
4274 ha->mem_ptr = NULL; in ips_free()
4518 isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isinit_copperhead_memio()
4519 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); in ips_isinit_copperhead_memio()
4547 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_isinit_morpheus()
4548 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isinit_morpheus()
4676 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_enable_int_copperhead_memio()
4677 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ in ips_enable_int_copperhead_memio()
4695 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4697 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4698 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ in ips_enable_int_morpheus()
4817 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4829 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4830 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4843 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4855 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4856 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4860 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); in ips_init_copperhead_memio()
4874 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); in ips_init_copperhead_memio()
4877 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); in ips_init_copperhead_memio()
4881 writel(0, ha->mem_ptr + IPS_REG_NDAE); in ips_init_copperhead_memio()
4884 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4912 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4929 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4937 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4940 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4957 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4968 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4985 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_morpheus()
4989 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4992 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
4994 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
5076 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5081 writeb(0, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5122 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); in ips_reset_morpheus()
5193 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); in ips_statinit_memio()
5195 ha->mem_ptr + IPS_REG_SQER); in ips_statinit_memio()
5196 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); in ips_statinit_memio()
5197 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); in ips_statinit_memio()
5252 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); in ips_statupd_copperhead_memio()
5273 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); in ips_statupd_morpheus()
5363 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { in ips_issue_copperhead_memio()
5379 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); in ips_issue_copperhead_memio()
5380 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); in ips_issue_copperhead_memio()
5444 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); in ips_issue_i2o_memio()
5498 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5509 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5531 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isintr_morpheus()
6189 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6193 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6198 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6203 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6208 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6216 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6220 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6234 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6242 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6246 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6270 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6275 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6395 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6399 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6403 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6411 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6415 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6426 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6430 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6440 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6444 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6453 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6457 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6531 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6535 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_verify_bios_memio()
6538 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6541 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_verify_bios_memio()
6547 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6552 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); in ips_verify_bios_memio()
6899 char __iomem *mem_ptr; in ips_init_phase1() local
6947 mem_ptr = ioremap_ptr + offs; in ips_init_phase1()
6950 mem_ptr = NULL; in ips_init_phase1()
6970 ha->mem_ptr = mem_ptr; in ips_init_phase1()
7070 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_phase1()