Lines Matching refs:mr
304 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_dump_regs() local
310 ms, mr, md); in mesh_dump_regs()
313 (mr->count_hi << 8) + mr->count_lo, mr->sequence, in mesh_dump_regs()
314 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count, in mesh_dump_regs()
315 mr->exception, mr->error, mr->intr_mask, mr->interrupt, in mesh_dump_regs()
316 mr->sync_params); in mesh_dump_regs()
317 while(in_8(&mr->fifo_count)) in mesh_dump_regs()
318 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo)); in mesh_dump_regs()
338 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr) in mesh_flush_io() argument
340 (void)in_8(&mr->mesh_id); in mesh_flush_io()
359 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_init() local
362 mesh_flush_io(mr); in mesh_init()
367 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_init()
368 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_init()
369 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_init()
370 mesh_flush_io(mr); in mesh_init()
372 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_init()
373 out_8(&mr->source_id, ms->host->this_id); in mesh_init()
374 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_init()
375 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
381 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_init()
382 mesh_flush_io(mr); in mesh_init()
384 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_init()
385 mesh_flush_io(mr); in mesh_init()
392 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ in mesh_init()
393 out_8(&mr->sequence, SEQ_FLUSHFIFO); in mesh_init()
394 mesh_flush_io(mr); in mesh_init()
396 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
397 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_init()
406 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_start_cmd() local
445 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
446 out_8(&mr->interrupt, INT_CMDDONE); in mesh_start_cmd()
447 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
448 mesh_flush_io(mr); in mesh_start_cmd()
451 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
457 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
458 mr->error, mr->fifo_count)); in mesh_start_cmd()
460 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0) in mesh_start_cmd()
462 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
464 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
465 mr->error, mr->fifo_count)); in mesh_start_cmd()
472 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
485 out_8(&mr->dest_id, mr->source_id); in mesh_start_cmd()
499 out_8(&mr->sequence, SEQ_DISRESEL); in mesh_start_cmd()
500 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
502 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
503 mr->error, mr->fifo_count)); in mesh_start_cmd()
508 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
509 mr->error, mr->fifo_count)); in mesh_start_cmd()
512 out_8(&mr->sequence, SEQ_ARBITRATE); in mesh_start_cmd()
515 if (in_8(&mr->interrupt) != 0) in mesh_start_cmd()
520 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
521 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
522 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
525 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
526 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_start_cmd()
527 mesh_flush_io(mr); in mesh_start_cmd()
529 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
530 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
531 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
532 mesh_flush_io(mr); in mesh_start_cmd()
533 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t) in mesh_start_cmd()
536 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
538 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
539 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
640 volatile struct mesh_regs __iomem *mr = ms->mesh; in set_sdtr() local
650 out_8(&mr->sync_params, ASYNC_PARAMS); in set_sdtr()
673 out_8(&mr->sync_params, tp->sync_params); in set_sdtr()
681 volatile struct mesh_regs __iomem *mr = ms->mesh; in start_phase() local
687 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence)); in start_phase()
688 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in start_phase()
695 out_8(&mr->count_hi, 0); in start_phase()
696 out_8(&mr->count_lo, 1); in start_phase()
697 out_8(&mr->sequence, SEQ_MSGIN + seq); in start_phase()
723 out_8(&mr->count_hi, 0); in start_phase()
724 out_8(&mr->sequence, SEQ_FLUSHFIFO); in start_phase()
725 mesh_flush_io(mr); in start_phase()
731 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) { in start_phase()
732 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0); in start_phase()
733 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */ in start_phase()
734 mesh_flush_io(mr); in start_phase()
736 out_8(&mr->count_lo, 1); in start_phase()
737 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
738 out_8(&mr->bus_status0, 0); /* release explicit ATN */ in start_phase()
739 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0); in start_phase()
750 out_8(&mr->count_lo, ms->n_msgout - 1); in start_phase()
751 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
753 out_8(&mr->fifo, ms->msgout[i]); in start_phase()
764 out_8(&mr->dest_id, ms->conn_tgt); in start_phase()
765 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN); in start_phase()
768 out_8(&mr->sync_params, tp->sync_params); in start_phase()
769 out_8(&mr->count_hi, 0); in start_phase()
771 out_8(&mr->count_lo, cmd->cmd_len); in start_phase()
772 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
774 out_8(&mr->fifo, cmd->cmnd[i]); in start_phase()
776 out_8(&mr->count_lo, 6); in start_phase()
777 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
779 out_8(&mr->fifo, 0); in start_phase()
795 out_8(&mr->count_lo, nb); in start_phase()
796 out_8(&mr->count_hi, nb >> 8); in start_phase()
797 out_8(&mr->sequence, (tp->data_goes_out? in start_phase()
801 out_8(&mr->count_hi, 0); in start_phase()
802 out_8(&mr->count_lo, 1); in start_phase()
803 out_8(&mr->sequence, SEQ_STATUS + seq); in start_phase()
807 out_8(&mr->sequence, SEQ_ENBRESEL); in start_phase()
808 mesh_flush_io(mr); in start_phase()
811 MKWORD(mr->interrupt, mr->exception, mr->error, in start_phase()
812 mr->fifo_count)); in start_phase()
813 out_8(&mr->sequence, SEQ_BUSFREE); in start_phase()
825 volatile struct mesh_regs __iomem *mr = ms->mesh; in get_msgin() local
828 n = mr->fifo_count; in get_msgin()
833 ms->msgin[i++] = in_8(&mr->fifo); in get_msgin()
857 volatile struct mesh_regs __iomem *mr = ms->mesh; in reselected() local
903 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) { in reselected()
906 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
907 mesh_flush_io(mr); in reselected()
909 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
910 mesh_flush_io(mr); in reselected()
913 MKWORD(0, mr->error, mr->exception, mr->fifo_count)); in reselected()
915 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
916 mesh_flush_io(mr); in reselected()
918 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
919 mesh_flush_io(mr); in reselected()
921 out_8(&mr->sync_params, ASYNC_PARAMS); in reselected()
926 if (in_8(&mr->fifo_count) == 0) { in reselected()
933 b = in_8(&mr->fifo); in reselected()
935 } while (in_8(&mr->fifo_count)); in reselected()
951 out_8(&mr->sync_params, tp->sync_params); in reselected()
964 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception)); in reselected()
990 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_reset() local
1010 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_reset()
1011 out_8(&mr->sequence, SEQ_FLUSHFIFO); in handle_reset()
1012 mesh_flush_io(mr); in handle_reset()
1014 out_8(&mr->sync_params, ASYNC_PARAMS); in handle_reset()
1015 out_8(&mr->sequence, SEQ_ENBRESEL); in handle_reset()
1033 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_error() local
1035 err = in_8(&mr->error); in handle_error()
1036 exc = in_8(&mr->exception); in handle_error()
1037 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_error()
1039 MKWORD(err, exc, mr->fifo_count, mr->count_lo)); in handle_error()
1044 while ((in_8(&mr->bus_status1) & BS1_RST) != 0) in handle_error()
1063 out_8(&mr->interrupt, INT_CMDDONE); in handle_error()
1083 count = (mr->count_hi << 8) + mr->count_lo; in handle_error()
1088 out_8(&mr->sequence, mr->sequence); in handle_error()
1114 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) { in handle_error()
1127 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_exception() local
1129 exc = in_8(&mr->exception); in handle_exception()
1130 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE); in handle_exception()
1321 volatile struct mesh_regs __iomem *mr = ms->mesh; in halt_dma() local
1328 while (t > 0 && in_8(&mr->fifo_count) != 0 in halt_dma()
1335 nb = (mr->count_hi << 8) + mr->count_lo; in halt_dma()
1337 MKWORD(0, mr->fifo_count, 0, nb)); in halt_dma()
1339 nb += mr->fifo_count; in halt_dma()
1365 volatile struct mesh_regs __iomem *mr = ms->mesh; in phase_mismatch() local
1369 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count)); in phase_mismatch()
1370 phase = in_8(&mr->bus_status0) & BS0_PHASE; in phase_mismatch()
1373 out_8(&mr->count_lo, 1); in phase_mismatch()
1374 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in phase_mismatch()
1375 mesh_flush_io(mr); in phase_mismatch()
1377 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in phase_mismatch()
1390 if (mr->fifo_count) { in phase_mismatch()
1391 out_8(&mr->sequence, SEQ_FLUSHFIFO); in phase_mismatch()
1392 mesh_flush_io(mr); in phase_mismatch()
1444 volatile struct mesh_regs __iomem *mr = ms->mesh; in cmd_complete() local
1449 dlog(ms, "cmd_complete fc=%x", mr->fifo_count); in cmd_complete()
1463 out_8(&mr->count_lo, n - ms->n_msgin); in cmd_complete()
1464 out_8(&mr->sequence, SEQ_MSGIN + seq); in cmd_complete()
1473 out_8(&mr->sequence, SEQ_FLUSHFIFO); in cmd_complete()
1474 mesh_flush_io(mr); in cmd_complete()
1476 out_8(&mr->count_lo, 1); in cmd_complete()
1477 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg); in cmd_complete()
1492 out_8(&mr->count_lo, 1); in cmd_complete()
1493 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN); in cmd_complete()
1495 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0) in cmd_complete()
1498 MKWORD(mr->error, mr->exception, in cmd_complete()
1499 mr->fifo_count, mr->count_lo)); in cmd_complete()
1500 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) { in cmd_complete()
1504 if (in_8(&mr->interrupt) & INT_ERROR) { in cmd_complete()
1506 in_8(&mr->error)); in cmd_complete()
1510 if (in_8(&mr->exception) != EXC_PHASEMM) in cmd_complete()
1512 in_8(&mr->exception)); in cmd_complete()
1515 in_8(&mr->bus_status0)); in cmd_complete()
1519 if (in_8(&mr->bus_status0) & BS0_REQ) { in cmd_complete()
1520 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in cmd_complete()
1521 mesh_flush_io(mr); in cmd_complete()
1523 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in cmd_complete()
1526 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN); in cmd_complete()
1568 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) { in cmd_complete()
1592 out_8(&mr->sequence, 0); in cmd_complete()
1593 out_8(&mr->interrupt, in cmd_complete()
1599 cmd->SCp.Status = mr->fifo; in cmd_complete()
1658 volatile struct mesh_regs __iomem *mr = ms->mesh; in DEF_SCSI_QCMD() local
1664 "phase=%d msgphase=%d\n", mr->bus_status0, in DEF_SCSI_QCMD()
1665 mr->interrupt, mr->exception, mr->error, in DEF_SCSI_QCMD()
1668 while ((intr = in_8(&mr->interrupt)) != 0) { in DEF_SCSI_QCMD()
1670 MKWORD(intr, mr->error, mr->exception, mr->sequence)); in DEF_SCSI_QCMD()
1676 out_8(&mr->interrupt, INT_CMDDONE); in DEF_SCSI_QCMD()
1706 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_host_reset() local
1716 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_host_reset()
1717 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_host_reset()
1718 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_host_reset()
1719 mesh_flush_io(mr); in mesh_host_reset()
1721 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_host_reset()
1722 out_8(&mr->source_id, ms->host->this_id); in mesh_host_reset()
1723 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_host_reset()
1724 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_host_reset()
1727 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_host_reset()
1728 mesh_flush_io(mr); in mesh_host_reset()
1730 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_host_reset()
1814 volatile struct mesh_regs __iomem *mr; in mesh_shutdown() local
1819 mr = ms->mesh; in mesh_shutdown()
1820 out_8(&mr->intr_mask, 0); in mesh_shutdown()
1821 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_shutdown()
1822 out_8(&mr->bus_status1, BS1_RST); in mesh_shutdown()
1823 mesh_flush_io(mr); in mesh_shutdown()
1825 out_8(&mr->bus_status1, 0); in mesh_shutdown()