Lines Matching refs:UARTDM_CSR_ADDR
67 #define UARTDM_CSR_ADDR 0x8 macro
512 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_75); in msm_hs_set_bps_locked()
516 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_150); in msm_hs_set_bps_locked()
520 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_300); in msm_hs_set_bps_locked()
524 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_600); in msm_hs_set_bps_locked()
528 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_1200); in msm_hs_set_bps_locked()
532 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400); in msm_hs_set_bps_locked()
536 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_3600); in msm_hs_set_bps_locked()
540 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_4800); in msm_hs_set_bps_locked()
544 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_7200); in msm_hs_set_bps_locked()
548 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_9600); in msm_hs_set_bps_locked()
552 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_14400); in msm_hs_set_bps_locked()
556 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_19200); in msm_hs_set_bps_locked()
560 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_28800); in msm_hs_set_bps_locked()
564 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_57600); in msm_hs_set_bps_locked()
568 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200); in msm_hs_set_bps_locked()
581 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200); in msm_hs_set_bps_locked()
585 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400); in msm_hs_set_bps_locked()