Lines Matching refs:BIT0
215 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
383 #define MASK_FRAMING BIT0
425 #define IRQ_MASTER BIT0
1882 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1885 else if (status & BIT0) in rx_async()
1892 else if (status & BIT0) in rx_async()
2105 if (status & BIT0) { in ri_change()
3911 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3924 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
4032 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
4035 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
4081 wr_reg32(info, TDCSR, BIT2 + BIT0); in tx_start()
4180 val |= BIT0; in async_mode()
4217 val |= BIT0; in async_mode()
4253 val = BIT15 + BIT14 + BIT0; in async_mode()
4342 val |= BIT0; in sync_mode()
4405 val |= BIT0; in sync_mode()
4441 val |= BIT1 + BIT0; in sync_mode()
4489 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); in sync_mode()
4553 if (status & BIT0) in get_signals()
4595 val |= BIT0; in msc_set_vcr()
4717 if (framesize < (2 + crc_size) || status & BIT0) { in rx_get_frame()
4841 if (count && (rd_reg32(info, TDCSR) & BIT0)) in free_tbuf_count()
4884 if (reg_value & BIT0) in tbuf_bytes()