Lines Matching refs:BIT1
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
382 #define MASK_PARITY BIT1
1882 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1883 if (status & BIT1) in rx_async()
1890 if (status & BIT1) in rx_async()
2068 if (status & BIT1) { in dcd_change()
3907 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3920 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
3984 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop()
4009 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start()
4042 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); in rx_start()
4052 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
4095 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
4441 val |= BIT1 + BIT0; in sync_mode()
4551 if (status & BIT1) in get_signals()
4593 val |= BIT1; in msc_set_vcr()
4709 status &= ~BIT1; in rx_get_frame()
4720 } else if (status & BIT1) { in rx_get_frame()
4764 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; in rx_get_frame()
5006 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()