88 	struct ci_hdrc				*ci;  member
212 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)  in ci_role()  argument
214 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);  in ci_role()
215 	return ci->roles[ci->role];  in ci_role()
218 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)  in ci_role_start()  argument
225 	if (!ci->roles[role])  in ci_role_start()
228 	ret = ci->roles[role]->start(ci);  in ci_role_start()
230 		ci->role = role;  in ci_role_start()
234 static inline void ci_role_stop(struct ci_hdrc *ci)  in ci_role_stop()  argument
236 	enum ci_role role = ci->role;  in ci_role_stop()
241 	ci->role = CI_ROLE_END;  in ci_role_stop()
243 	ci->roles[role]->stop(ci);  in ci_role_stop()
254 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)  in hw_read()  argument
256 	return ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_read()
270 static inline void __hw_write(struct ci_hdrc *ci, u32 val,  in __hw_write()  argument
273 	if (ci->imx28_write_fix)  in __hw_write()
286 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_write()  argument
290 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)  in hw_write()
293 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);  in hw_write()
304 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_test_and_clear()  argument
307 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_test_and_clear()
309 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);  in hw_test_and_clear()
322 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_test_and_write()  argument
325 	u32 val = hw_read(ci, reg, ~0);  in hw_test_and_write()
327 	hw_write(ci, reg, mask, data);  in hw_test_and_write()
337 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)  in ci_otg_is_fsm_mode()  argument
340 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&  in ci_otg_is_fsm_mode()
341 					ci->roles[CI_ROLE_GADGET];  in ci_otg_is_fsm_mode()
347 u32 hw_read_intr_enable(struct ci_hdrc *ci);
349 u32 hw_read_intr_status(struct ci_hdrc *ci);
351 int hw_device_reset(struct ci_hdrc *ci, u32 mode);
353 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
355 u8 hw_port_test_get(struct ci_hdrc *ci);
357 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,