Lines Matching defs:dwc2_hsotg

594 struct dwc2_hsotg {  struct
595 	struct device *dev;
596 	void __iomem *regs;
598 	struct dwc2_hw_params hw_params;
600 	struct dwc2_core_params *core_params;
601 	enum usb_otg_state op_state;
602 	enum usb_dr_mode dr_mode;
604 	unsigned int queuing_high_bandwidth:1;
605 	unsigned int srp_success:1;
607 	struct workqueue_struct *wq_otg;
608 	struct work_struct wf_otg;
609 	struct timer_list wkp_timer;
610 	enum dwc2_lx_state lx_state;
612 	union dwc2_hcd_internal_flags {
624 	} flags;
626 	struct list_head non_periodic_sched_inactive;
627 	struct list_head non_periodic_sched_active;
628 	struct list_head *non_periodic_qh_ptr;
629 	struct list_head periodic_sched_inactive;
630 	struct list_head periodic_sched_ready;
631 	struct list_head periodic_sched_assigned;
632 	struct list_head periodic_sched_queued;
633 	u16 periodic_usecs;
634 	u16 frame_usecs[8];
635 	u16 frame_number;
636 	u16 periodic_qh_count;
640 	u16 last_frame_num;
641 	u16 *frame_num_array;
642 	u16 *last_frame_num_array;
643 	int frame_num_idx;
644 	int dumped_frame_num_array;
647 	struct list_head free_hc_list;
648 	int periodic_channels;
649 	int non_periodic_channels;
650 	int available_host_channels;
651 	struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
652 	u8 *status_buf;
653 	dma_addr_t status_buf_dma;
656 	struct delayed_work start_work;
657 	struct delayed_work reset_work;
658 	spinlock_t lock;
659 	void *priv;
660 	u8 otg_port;
661 	u32 *frame_list;
662 	dma_addr_t frame_list_dma;
672 	u32 frrem_samples;
673 	u64 frrem_accum;
675 	u32 hfnum_7_samples_a;
676 	u64 hfnum_7_frrem_accum_a;
677 	u32 hfnum_0_samples_a;
678 	u64 hfnum_0_frrem_accum_a;
679 	u32 hfnum_other_samples_a;
680 	u64 hfnum_other_frrem_accum_a;
682 	u32 hfnum_7_samples_b;
683 	u64 hfnum_7_frrem_accum_b;
684 	u32 hfnum_0_samples_b;
685 	u64 hfnum_0_frrem_accum_b;
686 	u32 hfnum_other_samples_b;
687 	u64 hfnum_other_frrem_accum_b;