Lines Matching refs:cinfo
381 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
382 static void WGen(const struct cirrusfb_info *cinfo,
384 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
385 static void AttrOn(const struct cirrusfb_info *cinfo);
386 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
387 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
388 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
389 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
392 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
421 static inline int is_laguna(const struct cirrusfb_info *cinfo) in is_laguna() argument
423 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB; in is_laguna()
451 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_mclk() local
452 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; in cirrusfb_check_mclk()
478 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_pixclock() local
486 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx]; in cirrusfb_check_pixclock()
487 cinfo->multiplexing = 0; in cirrusfb_check_pixclock()
502 switch (cinfo->btype) { in cirrusfb_check_pixclock()
507 cinfo->multiplexing = 1; in cirrusfb_check_pixclock()
511 cinfo->multiplexing = 1; in cirrusfb_check_pixclock()
521 cinfo->doubleVCLK = 0; in cirrusfb_check_pixclock()
522 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ && in cirrusfb_check_pixclock()
524 cinfo->doubleVCLK = 1; in cirrusfb_check_pixclock()
536 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_var() local
626 if (!is_laguna(cinfo)) in cirrusfb_check_var()
634 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_mclk_as_source() local
637 assert(cinfo != NULL); in cirrusfb_set_mclk_as_source()
638 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; in cirrusfb_set_mclk_as_source()
644 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; in cirrusfb_set_mclk_as_source()
648 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); in cirrusfb_set_mclk_as_source()
650 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f); in cirrusfb_set_mclk_as_source()
660 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_par_foo() local
662 u8 __iomem *regbase = cinfo->regbase; in cirrusfb_set_par_foo()
697 bi = &cirrusfb_board_info[cinfo->btype]; in cirrusfb_set_par_foo()
735 if (cinfo->multiplexing) { in cirrusfb_set_par_foo()
838 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) in cirrusfb_set_par_foo()
840 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
842 if (cinfo->doubleVCLK) in cirrusfb_set_par_foo()
855 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 || in cirrusfb_set_par_foo()
856 cinfo->btype == BT_SD64) { in cirrusfb_set_par_foo()
865 if (is_laguna(cinfo)) { in cirrusfb_set_par_foo()
866 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc); in cirrusfb_set_par_foo()
867 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
870 if (cinfo->btype == BT_LAGUNAB) { in cirrusfb_set_par_foo()
871 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4); in cirrusfb_set_par_foo()
873 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4); in cirrusfb_set_par_foo()
876 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc); in cirrusfb_set_par_foo()
877 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
878 control = fb_readw(cinfo->laguna_mmio + 0x402); in cirrusfb_set_par_foo()
879 threshold = fb_readw(cinfo->laguna_mmio + 0xea); in cirrusfb_set_par_foo()
889 if ((cinfo->btype == BT_SD64) || in cirrusfb_set_par_foo()
890 (cinfo->btype == BT_ALPINE) || in cirrusfb_set_par_foo()
891 (cinfo->btype == BT_GD5480)) in cirrusfb_set_par_foo()
895 if (is_laguna(cinfo)) { in cirrusfb_set_par_foo()
926 WGen(cinfo, VGA_MIS_W, tmp); in cirrusfb_set_par_foo()
945 switch (cinfo->btype) { in cirrusfb_set_par_foo()
954 cinfo->multiplexing ? in cirrusfb_set_par_foo()
970 switch (cinfo->btype) { in cirrusfb_set_par_foo()
998 WGen(cinfo, VGA_PEL_MSK, 0x01); in cirrusfb_set_par_foo()
999 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
1001 WHDR(cinfo, 0x4a); in cirrusfb_set_par_foo()
1004 WHDR(cinfo, 0); in cirrusfb_set_par_foo()
1019 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1028 cinfo->multiplexing ? in cirrusfb_set_par_foo()
1044 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1072 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
1074 WHDR(cinfo, 0x4a); in cirrusfb_set_par_foo()
1077 WHDR(cinfo, 0); in cirrusfb_set_par_foo()
1088 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1107 cinfo->doubleVCLK ? 0xa3 : 0xa7); in cirrusfb_set_par_foo()
1132 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1); in cirrusfb_set_par_foo()
1135 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */ in cirrusfb_set_par_foo()
1147 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1190 WHDR(cinfo, 0xc5); in cirrusfb_set_par_foo()
1214 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) in cirrusfb_set_par_foo()
1217 if (is_laguna(cinfo)) { in cirrusfb_set_par_foo()
1241 AttrOn(cinfo); in cirrusfb_set_par_foo()
1243 if (is_laguna(cinfo)) { in cirrusfb_set_par_foo()
1245 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402); in cirrusfb_set_par_foo()
1246 fb_writew(format, cinfo->laguna_mmio + 0xc0); in cirrusfb_set_par_foo()
1247 fb_writew(threshold, cinfo->laguna_mmio + 0xea); in cirrusfb_set_par_foo()
1280 struct cirrusfb_info *cinfo = info->par; in cirrusfb_setcolreg() local
1297 cinfo->pseudo_palette[regno] = v; in cirrusfb_setcolreg()
1302 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10); in cirrusfb_setcolreg()
1319 struct cirrusfb_info *cinfo = info->par; in cirrusfb_pan_display() local
1338 if (!is_laguna(cinfo)) in cirrusfb_pan_display()
1339 cirrusfb_WaitBLT(cinfo->regbase); in cirrusfb_pan_display()
1342 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff); in cirrusfb_pan_display()
1343 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff); in cirrusfb_pan_display()
1346 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2; in cirrusfb_pan_display()
1355 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp); in cirrusfb_pan_display()
1358 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) { in cirrusfb_pan_display()
1359 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D); in cirrusfb_pan_display()
1360 if (is_laguna(cinfo)) in cirrusfb_pan_display()
1364 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp); in cirrusfb_pan_display()
1372 vga_wattr(cinfo->regbase, CL_AR33, xpix); in cirrusfb_pan_display()
1391 struct cirrusfb_info *cinfo = info->par; in cirrusfb_blank() local
1392 int current_mode = cinfo->blank_mode; in cirrusfb_blank()
1411 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf; in cirrusfb_blank()
1412 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val); in cirrusfb_blank()
1433 vga_wgfx(cinfo->regbase, CL_GRE, val); in cirrusfb_blank()
1435 cinfo->blank_mode = blank_mode; in cirrusfb_blank()
1448 struct cirrusfb_info *cinfo = info->par; in init_vgachip() local
1451 assert(cinfo != NULL); in init_vgachip()
1453 bi = &cirrusfb_board_info[cinfo->btype]; in init_vgachip()
1456 switch (cinfo->btype) { in init_vgachip()
1458 WSFR(cinfo, 0x01); in init_vgachip()
1460 WSFR(cinfo, 0x51); in init_vgachip()
1464 WSFR2(cinfo, 0xff); in init_vgachip()
1469 WSFR(cinfo, 0x1f); in init_vgachip()
1471 WSFR(cinfo, 0x4f); in init_vgachip()
1476 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00); in init_vgachip()
1479 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1482 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00); in init_vgachip()
1485 vga_wgfx(cinfo->regbase, CL_GR33, 0x00); in init_vgachip()
1505 if (cinfo->btype != BT_PICASSO4) { in init_vgachip()
1506 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */ in init_vgachip()
1507 WGen(cinfo, CL_POS102, 0x01); in init_vgachip()
1508 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */ in init_vgachip()
1510 if (cinfo->btype != BT_SD64) in init_vgachip()
1511 WGen(cinfo, CL_VSSM2, 0x01); in init_vgachip()
1514 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03); in init_vgachip()
1517 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); in init_vgachip()
1522 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12); in init_vgachip()
1524 switch (cinfo->btype) { in init_vgachip()
1526 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98); in init_vgachip()
1534 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8); in init_vgachip()
1538 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f); in init_vgachip()
1539 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0); in init_vgachip()
1544 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); in init_vgachip()
1546 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); in init_vgachip()
1548 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a); in init_vgachip()
1552 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07); in init_vgachip()
1558 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00); in init_vgachip()
1560 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00); in init_vgachip()
1562 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00); in init_vgachip()
1564 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00); in init_vgachip()
1567 if (cinfo->btype != BT_PICASSO4) { in init_vgachip()
1569 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00); in init_vgachip()
1571 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02); in init_vgachip()
1575 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); in init_vgachip()
1577 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); in init_vgachip()
1579 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); in init_vgachip()
1581 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); in init_vgachip()
1583 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); in init_vgachip()
1586 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); in init_vgachip()
1589 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02); in init_vgachip()
1592 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); in init_vgachip()
1594 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); in init_vgachip()
1596 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); in init_vgachip()
1598 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); in init_vgachip()
1600 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); in init_vgachip()
1602 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00); in init_vgachip()
1604 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01); in init_vgachip()
1606 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); in init_vgachip()
1608 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); in init_vgachip()
1610 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 || in init_vgachip()
1611 is_laguna(cinfo)) in init_vgachip()
1613 vga_wgfx(cinfo->regbase, CL_GRB, 0x20); in init_vgachip()
1618 vga_wgfx(cinfo->regbase, CL_GRB, 0x28); in init_vgachip()
1620 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */ in init_vgachip()
1621 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */ in init_vgachip()
1622 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */ in init_vgachip()
1628 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00); in init_vgachip()
1629 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01); in init_vgachip()
1630 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02); in init_vgachip()
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03); in init_vgachip()
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04); in init_vgachip()
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05); in init_vgachip()
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06); in init_vgachip()
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07); in init_vgachip()
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08); in init_vgachip()
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09); in init_vgachip()
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a); in init_vgachip()
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b); in init_vgachip()
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c); in init_vgachip()
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d); in init_vgachip()
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e); in init_vgachip()
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f); in init_vgachip()
1646 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01); in init_vgachip()
1648 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); in init_vgachip()
1650 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); in init_vgachip()
1652 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); in init_vgachip()
1654 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */ in init_vgachip()
1657 vga_wgfx(cinfo->regbase, CL_GR31, 0x04); in init_vgachip()
1659 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1662 WHDR(cinfo, 0); /* Hidden DAC register: - */ in init_vgachip()
1666 static void switch_monitor(struct cirrusfb_info *cinfo, int on) in switch_monitor() argument
1671 if (cinfo->btype == BT_PICASSO4) in switch_monitor()
1673 if (cinfo->btype == BT_ALPINE) in switch_monitor()
1675 if (cinfo->btype == BT_GD5480) in switch_monitor()
1677 if (cinfo->btype == BT_PICASSO) { in switch_monitor()
1679 WSFR(cinfo, 0xff); in switch_monitor()
1683 switch (cinfo->btype) { in switch_monitor()
1685 WSFR(cinfo, cinfo->SFR | 0x21); in switch_monitor()
1688 WSFR(cinfo, cinfo->SFR | 0x28); in switch_monitor()
1691 WSFR(cinfo, 0x6f); in switch_monitor()
1696 switch (cinfo->btype) { in switch_monitor()
1698 WSFR(cinfo, cinfo->SFR & 0xde); in switch_monitor()
1701 WSFR(cinfo, cinfo->SFR & 0xd7); in switch_monitor()
1704 WSFR(cinfo, 0x4f); in switch_monitor()
1719 struct cirrusfb_info *cinfo = info->par; in cirrusfb_sync() local
1721 if (!is_laguna(cinfo)) { in cirrusfb_sync()
1722 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03) in cirrusfb_sync()
1733 struct cirrusfb_info *cinfo = info->par; in cirrusfb_fillrect() local
1736 cinfo->pseudo_palette[region->color] : region->color; in cirrusfb_fillrect()
1759 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_fillrect()
1772 struct cirrusfb_info *cinfo = info->par; in cirrusfb_copyarea() local
1800 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel, in cirrusfb_copyarea()
1811 struct cirrusfb_info *cinfo = info->par; in cirrusfb_imageblit() local
1819 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) && in cirrusfb_imageblit()
1836 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_imageblit()
1844 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_imageblit()
1865 struct cirrusfb_info *cinfo = info->par; in cirrusfb_get_memsize() local
1867 if (is_laguna(cinfo)) { in cirrusfb_get_memsize()
1893 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0) in cirrusfb_get_memsize()
1927 struct cirrusfb_info *cinfo = info->par; in cirrusfb_pci_unmap() local
1929 if (cinfo->laguna_mmio == NULL) in cirrusfb_pci_unmap()
1930 iounmap(cinfo->laguna_mmio); in cirrusfb_pci_unmap()
1944 struct cirrusfb_info *cinfo = info->par; in cirrusfb_zorro_unmap() local
1950 iounmap(cinfo->regbase); in cirrusfb_zorro_unmap()
1974 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_fbinfo() local
1977 info->pseudo_palette = cinfo->pseudo_palette; in cirrusfb_set_fbinfo()
1984 if (noaccel || is_laguna(cinfo)) { in cirrusfb_set_fbinfo()
1992 if (cinfo->btype == BT_GD5480) { in cirrusfb_set_fbinfo()
2000 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name, in cirrusfb_set_fbinfo()
2023 struct cirrusfb_info *cinfo = info->par; in cirrusfb_register() local
2027 assert(cinfo->btype != BT_NONE); in cirrusfb_register()
2067 struct cirrusfb_info *cinfo = info->par; in cirrusfb_cleanup() local
2069 switch_monitor(cinfo, 0); in cirrusfb_cleanup()
2073 cinfo->unmap(info); in cirrusfb_cleanup()
2081 struct cirrusfb_info *cinfo; in cirrusfb_pci_register() local
2099 cinfo = info->par; in cirrusfb_pci_register()
2100 cinfo->btype = (enum cirrus_board) ent->driver_data; in cirrusfb_pci_register()
2104 (unsigned long long)pdev->resource[0].start, cinfo->btype); in cirrusfb_pci_register()
2112 cinfo->regbase = NULL; in cirrusfb_pci_register()
2113 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000); in cirrusfb_pci_register()
2118 board_size = (cinfo->btype == BT_GD5480) ? in cirrusfb_pci_register()
2119 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase); in cirrusfb_pci_register()
2146 cinfo->unmap = cirrusfb_pci_unmap; in cirrusfb_pci_register()
2167 if (cinfo->laguna_mmio != NULL) in cirrusfb_pci_register()
2168 iounmap(cinfo->laguna_mmio); in cirrusfb_pci_register()
2204 struct cirrusfb_info *cinfo; in cirrusfb_zorro_register() local
2254 cinfo = info->par; in cirrusfb_zorro_register()
2255 cinfo->btype = btype; in cirrusfb_zorro_register()
2258 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024) in cirrusfb_zorro_register()
2260 if (!cinfo->regbase) { in cirrusfb_zorro_register()
2276 cinfo->unmap = cirrusfb_zorro_unmap; in cirrusfb_zorro_register()
2284 vga_wseq(cinfo->regbase, CL_SEQR1F, in cirrusfb_zorro_register()
2303 iounmap(cinfo->regbase); in cirrusfb_zorro_register()
2408 static void WGen(const struct cirrusfb_info *cinfo, in WGen() argument
2413 if (cinfo->btype == BT_PICASSO) { in WGen()
2421 vga_w(cinfo->regbase, regofs + regnum, val); in WGen()
2425 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum) in RGen() argument
2429 if (cinfo->btype == BT_PICASSO) { in RGen()
2437 return vga_r(cinfo->regbase, regofs + regnum); in RGen()
2441 static void AttrOn(const struct cirrusfb_info *cinfo) in AttrOn() argument
2443 assert(cinfo != NULL); in AttrOn()
2445 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) { in AttrOn()
2448 vga_w(cinfo->regbase, VGA_ATT_IW, in AttrOn()
2449 vga_r(cinfo->regbase, VGA_ATT_R)); in AttrOn()
2453 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33); in AttrOn()
2456 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00); in AttrOn()
2465 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val) in WHDR() argument
2469 if (is_laguna(cinfo)) in WHDR()
2471 if (cinfo->btype == BT_PICASSO) { in WHDR()
2474 WGen(cinfo, VGA_PEL_MSK, 0x00); in WHDR()
2477 dummy = RGen(cinfo, VGA_PEL_IW); in WHDR()
2482 dummy = RGen(cinfo, VGA_PEL_MSK); in WHDR()
2484 dummy = RGen(cinfo, VGA_PEL_MSK); in WHDR()
2486 dummy = RGen(cinfo, VGA_PEL_MSK); in WHDR()
2488 dummy = RGen(cinfo, VGA_PEL_MSK); in WHDR()
2491 WGen(cinfo, VGA_PEL_MSK, val); in WHDR()
2494 if (cinfo->btype == BT_PICASSO) { in WHDR()
2496 dummy = RGen(cinfo, VGA_PEL_IW); in WHDR()
2501 WGen(cinfo, VGA_PEL_MSK, 0xff); in WHDR()
2507 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val) in WSFR() argument
2510 assert(cinfo->regbase != NULL); in WSFR()
2511 cinfo->SFR = val; in WSFR()
2512 z_writeb(val, cinfo->regbase + 0x8000); in WSFR()
2517 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val) in WSFR2() argument
2522 assert(cinfo->regbase != NULL); in WSFR2()
2523 cinfo->SFR = val; in WSFR2()
2524 z_writeb(val, cinfo->regbase + 0x9000); in WSFR2()
2529 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red, in WClut() argument
2535 vga_w(cinfo->regbase, VGA_PEL_IW, regnum); in WClut()
2537 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || in WClut()
2538 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 || in WClut()
2539 cinfo->btype == BT_SD64 || is_laguna(cinfo)) { in WClut()
2541 if (cinfo->btype == BT_PICASSO) in WClut()
2543 vga_w(cinfo->regbase, data, red); in WClut()
2544 vga_w(cinfo->regbase, data, green); in WClut()
2545 vga_w(cinfo->regbase, data, blue); in WClut()
2547 vga_w(cinfo->regbase, data, blue); in WClut()
2548 vga_w(cinfo->regbase, data, green); in WClut()
2549 vga_w(cinfo->regbase, data, red); in WClut()
2555 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2560 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2562 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2563 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2564 if (cinfo->btype == BT_PICASSO)
2566 *red = vga_r(cinfo->regbase, data);
2567 *green = vga_r(cinfo->regbase, data);
2568 *blue = vga_r(cinfo->regbase, data);
2570 *blue = vga_r(cinfo->regbase, data);
2571 *green = vga_r(cinfo->regbase, data);
2572 *red = vga_r(cinfo->regbase, data);