38 #define write_reg(val, reg) do { writel((val), (reg)); } while(0)  macro
448 	write_reg(vsctrl, VSCTRL);  in mbxfb_setupOverlay()
449 	write_reg(vscadr, VSCADR);  in mbxfb_setupOverlay()
450 	write_reg(vubase, VUBASE);  in mbxfb_setupOverlay()
451 	write_reg(vvbase, VVBASE);  in mbxfb_setupOverlay()
452 	write_reg(vsadr, VSADR);  in mbxfb_setupOverlay()
455 	write_reg(sssize, SSSIZE);  in mbxfb_setupOverlay()
456 	write_reg(spoctrl, SPOCTRL);  in mbxfb_setupOverlay()
457 	write_reg(shctrl, SHCTRL);  in mbxfb_setupOverlay()
465 	write_reg(vovrclk, VOVRCLK);  in mbxfb_setupOverlay()
825 	write_reg(0xff000100, VSCOEFF0);  in enable_controller()
826 	write_reg(0xfdfcfdfe, VSCOEFF1);  in enable_controller()
827 	write_reg(0x170d0500, VSCOEFF2);  in enable_controller()
828 	write_reg(0x3d372d22, VSCOEFF3);  in enable_controller()
829 	write_reg(0x00000040, VSCOEFF4);  in enable_controller()
831 	write_reg(0xff010100, HSCOEFF0);  in enable_controller()
832 	write_reg(0x00000000, HSCOEFF1);  in enable_controller()
833 	write_reg(0x02010000, HSCOEFF2);  in enable_controller()
834 	write_reg(0x01020302, HSCOEFF3);  in enable_controller()
835 	write_reg(0xf9fbfe00, HSCOEFF4);  in enable_controller()
836 	write_reg(0xfbf7f6f7, HSCOEFF5);  in enable_controller()
837 	write_reg(0x1c110700, HSCOEFF6);  in enable_controller()
838 	write_reg(0x3e393127, HSCOEFF7);  in enable_controller()
839 	write_reg(0x00000040, HSCOEFF8);  in enable_controller()