Lines Matching refs:BIT0
59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
349 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
352 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
377 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
409 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
410 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
422 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
435 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
476 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0); in viafb_dvi_enable()