Lines Matching refs:uint32_t

34 		uint32_t raw;
36 			uint32_t valid:1;	/* Address captured */
37 			uint32_t master_id:4;	/* Unit causing error
45 			uint32_t mul_err:1;	/* Multiple errors occurred */
46 			uint32_t addr:26;	/* Bits 31-6 of error addr */
49 	uint32_t pci_err_addr_h;	/* Bits 63-32 of error addr */
51 		uint32_t raw;
64 		uint32_t raw;
66 			uint32_t ata_int:1;	/* ATA port passthru */
67 			uint32_t ata_memerr:1;	/* ATA halted by mem error */
68 			uint32_t memerr:4;	/* Serial halted by mem err */
69 			uint32_t kbd_int:1;	/* kbd/mouse intr asserted */
70 			uint32_t reserved:16;	/* zero */
71 			uint32_t rt_int:1;	/* INT_OUT section latch */
72 			uint32_t gen_int:8;	/* Intr. from generic pins */
80 		uint32_t raw;
82 			uint32_t cmd_pulse:4;	/* Bytebus strobe width */
83 			uint32_t arb_diag:3;	/* PCI bus requester */
84 			uint32_t sio_diag_idle:1;	/* Active ser req? */
85 			uint32_t ata_diag_idle:1;	/* Active ATA req? */
86 			uint32_t ata_diag_active:1;	/* ATA req is winner */
87 			uint32_t reserved:22;	/* zero */
90 	uint32_t unused1;
92 		uint32_t raw;
94 			uint32_t count:16;	/* Period control */
95 			uint32_t mode:3;	/* Output signal shape */
96 			uint32_t reserved:11;	/* zero */
97 			uint32_t diag:1;	/* Timebase control */
98 			uint32_t int_out:1;	/* Current value */
101 	uint32_t unused2;
103 		uint32_t raw;
105 			uint32_t dir:8;	/* Pin direction */
106 			uint32_t edge:8;	/* Edge/level mode */
107 			uint32_t reserved1:4;	/* zero */
108 			uint32_t int_out_en:1;	/* INT_OUT enable */
109 			uint32_t reserved2:11;	/* zero */
114 		uint32_t raw;
116 			uint32_t gen_pin:8;	/* State of pins */
117 			uint32_t reserved:24;
120 	uint32_t unused3;
122 		uint32_t raw;
124 			uint32_t gen_pin:1;	/* Single pin state */
125 			uint32_t reserved:31;