Lines Matching refs:azx_dev
57 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) in azx_stream_start() argument
62 azx_dev->insufficient = 1; in azx_stream_start()
66 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); in azx_stream_start()
68 azx_sd_writeb(chip, azx_dev, SD_CTL, in azx_stream_start()
69 azx_sd_readb(chip, azx_dev, SD_CTL) | in azx_stream_start()
74 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) in azx_stream_clear() argument
76 azx_sd_writeb(chip, azx_dev, SD_CTL, in azx_stream_clear()
77 azx_sd_readb(chip, azx_dev, SD_CTL) & in azx_stream_clear()
79 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ in azx_stream_clear()
83 void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) in azx_stream_stop() argument
85 azx_stream_clear(chip, azx_dev); in azx_stream_stop()
88 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); in azx_stream_stop()
93 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) in azx_stream_reset() argument
98 azx_stream_clear(chip, azx_dev); in azx_stream_reset()
100 azx_sd_writeb(chip, azx_dev, SD_CTL, in azx_stream_reset()
101 azx_sd_readb(chip, azx_dev, SD_CTL) | in azx_stream_reset()
105 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & in azx_stream_reset()
109 azx_sd_writeb(chip, azx_dev, SD_CTL, val); in azx_stream_reset()
114 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & in azx_stream_reset()
119 *azx_dev->posbuf = 0; in azx_stream_reset()
125 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) in azx_setup_controller() argument
129 azx_stream_clear(chip, azx_dev); in azx_setup_controller()
131 val = azx_sd_readl(chip, azx_dev, SD_CTL); in azx_setup_controller()
133 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); in azx_setup_controller()
136 azx_sd_writel(chip, azx_dev, SD_CTL, val); in azx_setup_controller()
139 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize); in azx_setup_controller()
143 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val); in azx_setup_controller()
146 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1); in azx_setup_controller()
150 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); in azx_setup_controller()
152 azx_sd_writel(chip, azx_dev, SD_BDLPU, in azx_setup_controller()
153 upper_32_bits(azx_dev->bdl.addr)); in azx_setup_controller()
164 azx_sd_writel(chip, azx_dev, SD_CTL, in azx_setup_controller()
165 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK); in azx_setup_controller()
171 static inline struct azx_dev *
175 struct azx_dev *res = NULL; in azx_assign_device()
188 struct azx_dev *azx_dev = &chip->azx_dev[dev]; in azx_assign_device() local
189 dsp_lock(azx_dev); in azx_assign_device()
190 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { in azx_assign_device()
191 if (azx_dev->assigned_key == key) { in azx_assign_device()
192 azx_dev->opened = 1; in azx_assign_device()
193 azx_dev->assigned_key = key; in azx_assign_device()
194 dsp_unlock(azx_dev); in azx_assign_device()
195 return azx_dev; in azx_assign_device()
199 res = azx_dev; in azx_assign_device()
201 dsp_unlock(azx_dev); in azx_assign_device()
213 static inline void azx_release_device(struct azx_dev *azx_dev) in azx_release_device() argument
215 azx_dev->opened = 0; in azx_release_device()
220 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); in azx_cc_read() local
221 struct snd_pcm_substream *substream = azx_dev->substream; in azx_cc_read()
231 struct azx_dev *azx_dev = get_azx_dev(substream); in azx_timecounter_init() local
232 struct timecounter *tc = &azx_dev->azx_tc; in azx_timecounter_init()
233 struct cyclecounter *cc = &azx_dev->azx_cc; in azx_timecounter_init()
287 struct azx_dev *azx_dev, u32 **bdlp, in setup_bdle() argument
296 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) in setup_bdle()
318 azx_dev->frags++; in setup_bdle()
330 struct azx_dev *azx_dev) in azx_setup_periods() argument
337 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); in azx_setup_periods()
338 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); in azx_setup_periods()
340 period_bytes = azx_dev->period_bytes; in azx_setup_periods()
341 periods = azx_dev->bufsize / period_bytes; in azx_setup_periods()
344 bdl = (u32 *)azx_dev->bdl.area; in azx_setup_periods()
346 azx_dev->frags = 0; in azx_setup_periods()
350 if (!azx_dev->no_period_wakeup && pos_adj > 0) { in azx_setup_periods()
366 azx_dev, in azx_setup_periods()
377 azx_dev, &bdl, ofs, in azx_setup_periods()
381 azx_dev, &bdl, ofs, in azx_setup_periods()
383 !azx_dev->no_period_wakeup); in azx_setup_periods()
391 azx_dev->bufsize, period_bytes); in azx_setup_periods()
404 struct azx_dev *azx_dev = get_azx_dev(substream); in azx_pcm_close() local
409 azx_dev->substream = NULL; in azx_pcm_close()
410 azx_dev->running = 0; in azx_pcm_close()
412 azx_release_device(azx_dev); in azx_pcm_close()
442 struct azx_dev *azx_dev = get_azx_dev(substream); in azx_pcm_hw_free() local
448 dsp_lock(azx_dev); in azx_pcm_hw_free()
449 if (!dsp_is_locked(azx_dev)) { in azx_pcm_hw_free()
450 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); in azx_pcm_hw_free()
451 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); in azx_pcm_hw_free()
452 azx_sd_writel(chip, azx_dev, SD_CTL, 0); in azx_pcm_hw_free()
453 azx_dev->bufsize = 0; in azx_pcm_hw_free()
454 azx_dev->period_bytes = 0; in azx_pcm_hw_free()
455 azx_dev->format_val = 0; in azx_pcm_hw_free()
461 azx_dev->prepared = 0; in azx_pcm_hw_free()
462 dsp_unlock(azx_dev); in azx_pcm_hw_free()
470 struct azx_dev *azx_dev = get_azx_dev(substream); in azx_pcm_prepare() local
479 dsp_lock(azx_dev); in azx_pcm_prepare()
480 if (dsp_is_locked(azx_dev)) { in azx_pcm_prepare()
485 azx_stream_reset(chip, azx_dev); in azx_pcm_prepare()
506 if (bufsize != azx_dev->bufsize || in azx_pcm_prepare()
507 period_bytes != azx_dev->period_bytes || in azx_pcm_prepare()
508 format_val != azx_dev->format_val || in azx_pcm_prepare()
509 runtime->no_period_wakeup != azx_dev->no_period_wakeup) { in azx_pcm_prepare()
510 azx_dev->bufsize = bufsize; in azx_pcm_prepare()
511 azx_dev->period_bytes = period_bytes; in azx_pcm_prepare()
512 azx_dev->format_val = format_val; in azx_pcm_prepare()
513 azx_dev->no_period_wakeup = runtime->no_period_wakeup; in azx_pcm_prepare()
514 err = azx_setup_periods(chip, substream, azx_dev); in azx_pcm_prepare()
524 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64); in azx_pcm_prepare()
526 azx_dev->delay_negative_threshold = 0; in azx_pcm_prepare()
529 azx_dev->period_wallclk = (((runtime->period_size * 24000) / in azx_pcm_prepare()
531 azx_setup_controller(chip, azx_dev); in azx_pcm_prepare()
533 azx_dev->fifo_size = in azx_pcm_prepare()
534 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1; in azx_pcm_prepare()
536 azx_dev->fifo_size = 0; in azx_pcm_prepare()
538 stream_tag = azx_dev->stream_tag; in azx_pcm_prepare()
544 azx_dev->format_val, substream); in azx_pcm_prepare()
548 azx_dev->prepared = 1; in azx_pcm_prepare()
549 dsp_unlock(azx_dev); in azx_pcm_prepare()
557 struct azx_dev *azx_dev; in azx_pcm_trigger() local
562 azx_dev = get_azx_dev(substream); in azx_pcm_trigger()
563 trace_azx_pcm_trigger(chip, azx_dev, cmd); in azx_pcm_trigger()
565 if (dsp_is_locked(azx_dev) || !azx_dev->prepared) in azx_pcm_trigger()
587 azx_dev = get_azx_dev(s); in azx_pcm_trigger()
588 sbits |= 1 << azx_dev->index; in azx_pcm_trigger()
605 azx_dev = get_azx_dev(s); in azx_pcm_trigger()
607 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); in azx_pcm_trigger()
609 azx_dev->start_wallclk -= in azx_pcm_trigger()
610 azx_dev->period_wallclk; in azx_pcm_trigger()
611 azx_stream_start(chip, azx_dev); in azx_pcm_trigger()
613 azx_stream_stop(chip, azx_dev); in azx_pcm_trigger()
615 azx_dev->running = start; in azx_pcm_trigger()
625 azx_dev = get_azx_dev(s); in azx_pcm_trigger()
626 if (!(azx_sd_readb(chip, azx_dev, SD_STS) & in azx_pcm_trigger()
641 azx_dev = get_azx_dev(s); in azx_pcm_trigger()
642 if (azx_sd_readb(chip, azx_dev, SD_CTL) & in azx_pcm_trigger()
664 azx_dev = get_azx_dev(substream); in azx_pcm_trigger()
665 cycle_last = azx_dev->azx_tc.cycle_last; in azx_pcm_trigger()
678 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev) in azx_get_pos_lpib() argument
680 return azx_sd_readl(chip, azx_dev, SD_LPIB); in azx_get_pos_lpib()
684 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev) in azx_get_pos_posbuf() argument
686 return le32_to_cpu(*azx_dev->posbuf); in azx_get_pos_posbuf()
691 struct azx_dev *azx_dev) in azx_get_position() argument
693 struct snd_pcm_substream *substream = azx_dev->substream; in azx_get_position()
699 pos = chip->get_position[stream](chip, azx_dev); in azx_get_position()
701 pos = azx_get_pos_posbuf(chip, azx_dev); in azx_get_position()
703 if (pos >= azx_dev->bufsize) in azx_get_position()
711 delay += chip->get_delay[stream](chip, azx_dev, pos); in azx_get_position()
718 trace_azx_get_position(chip, azx_dev, pos, delay); in azx_get_position()
727 struct azx_dev *azx_dev = get_azx_dev(substream); in azx_pcm_pointer() local
729 azx_get_position(chip, azx_dev)); in azx_pcm_pointer()
735 struct azx_dev *azx_dev = get_azx_dev(substream); in azx_get_wallclock_tstamp() local
738 nsec = timecounter_read(&azx_dev->azx_tc); in azx_get_wallclock_tstamp()
777 struct azx_dev *azx_dev; in azx_pcm_open() local
784 azx_dev = azx_assign_device(chip, substream); in azx_pcm_open()
785 if (azx_dev == NULL) { in azx_pcm_open()
824 azx_release_device(azx_dev); in azx_pcm_open()
835 azx_release_device(azx_dev); in azx_pcm_open()
848 azx_dev->substream = substream; in azx_pcm_open()
849 azx_dev->running = 0; in azx_pcm_open()
852 runtime->private_data = azx_dev; in azx_pcm_open()
1332 static struct azx_dev *
1335 return &chip->azx_dev[chip->playback_index_offset]; in azx_get_dsp_loader_dev()
1344 struct azx_dev *azx_dev; in azx_load_dsp_prepare() local
1347 azx_dev = azx_get_dsp_loader_dev(chip); in azx_load_dsp_prepare()
1349 dsp_lock(azx_dev); in azx_load_dsp_prepare()
1351 if (azx_dev->running || azx_dev->locked) { in azx_load_dsp_prepare()
1356 azx_dev->prepared = 0; in azx_load_dsp_prepare()
1357 chip->saved_azx_dev = *azx_dev; in azx_load_dsp_prepare()
1358 azx_dev->locked = 1; in azx_load_dsp_prepare()
1366 azx_dev->bufsize = byte_size; in azx_load_dsp_prepare()
1367 azx_dev->period_bytes = byte_size; in azx_load_dsp_prepare()
1368 azx_dev->format_val = format; in azx_load_dsp_prepare()
1370 azx_stream_reset(chip, azx_dev); in azx_load_dsp_prepare()
1373 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); in azx_load_dsp_prepare()
1374 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); in azx_load_dsp_prepare()
1376 azx_dev->frags = 0; in azx_load_dsp_prepare()
1377 bdl = (u32 *)azx_dev->bdl.area; in azx_load_dsp_prepare()
1378 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); in azx_load_dsp_prepare()
1382 azx_setup_controller(chip, azx_dev); in azx_load_dsp_prepare()
1383 dsp_unlock(azx_dev); in azx_load_dsp_prepare()
1384 return azx_dev->stream_tag; in azx_load_dsp_prepare()
1390 if (azx_dev->opened) in azx_load_dsp_prepare()
1391 *azx_dev = chip->saved_azx_dev; in azx_load_dsp_prepare()
1392 azx_dev->locked = 0; in azx_load_dsp_prepare()
1395 dsp_unlock(azx_dev); in azx_load_dsp_prepare()
1402 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); in azx_load_dsp_trigger() local
1405 azx_stream_start(chip, azx_dev); in azx_load_dsp_trigger()
1407 azx_stream_stop(chip, azx_dev); in azx_load_dsp_trigger()
1408 azx_dev->running = start; in azx_load_dsp_trigger()
1415 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); in azx_load_dsp_cleanup() local
1417 if (!dmab->area || !azx_dev->locked) in azx_load_dsp_cleanup()
1420 dsp_lock(azx_dev); in azx_load_dsp_cleanup()
1422 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); in azx_load_dsp_cleanup()
1423 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); in azx_load_dsp_cleanup()
1424 azx_sd_writel(chip, azx_dev, SD_CTL, 0); in azx_load_dsp_cleanup()
1425 azx_dev->bufsize = 0; in azx_load_dsp_cleanup()
1426 azx_dev->period_bytes = 0; in azx_load_dsp_cleanup()
1427 azx_dev->format_val = 0; in azx_load_dsp_cleanup()
1433 if (azx_dev->opened) in azx_load_dsp_cleanup()
1434 *azx_dev = chip->saved_azx_dev; in azx_load_dsp_cleanup()
1435 azx_dev->locked = 0; in azx_load_dsp_cleanup()
1437 dsp_unlock(azx_dev); in azx_load_dsp_cleanup()
1447 dsp_lock_init(&chip->azx_dev[i]); in azx_alloc_stream_pages()
1451 &chip->azx_dev[i].bdl); in azx_alloc_stream_pages()
1476 if (chip->azx_dev) { in azx_free_stream_pages()
1478 if (chip->azx_dev[i].bdl.area) in azx_free_stream_pages()
1480 chip, &chip->azx_dev[i].bdl); in azx_free_stream_pages()
1581 struct azx_dev *azx_dev = &chip->azx_dev[i]; in azx_int_disable() local
1582 azx_sd_writeb(chip, azx_dev, SD_CTL, in azx_int_disable()
1583 azx_sd_readb(chip, azx_dev, SD_CTL) & in azx_int_disable()
1602 struct azx_dev *azx_dev = &chip->azx_dev[i]; in azx_int_clear() local
1603 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); in azx_int_clear()
1669 struct azx_dev *azx_dev; in azx_interrupt() local
1694 azx_dev = &chip->azx_dev[i]; in azx_interrupt()
1695 if (status & azx_dev->sd_int_sta_mask) { in azx_interrupt()
1696 sd_status = azx_sd_readb(chip, azx_dev, SD_STS); in azx_interrupt()
1697 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); in azx_interrupt()
1698 if (!azx_dev->substream || !azx_dev->running || in azx_interrupt()
1703 chip->ops->position_check(chip, azx_dev)) { in azx_interrupt()
1705 snd_pcm_period_elapsed(azx_dev->substream); in azx_interrupt()
1930 struct azx_dev *azx_dev = &chip->azx_dev[i]; in azx_init_stream() local
1931 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); in azx_init_stream()
1933 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); in azx_init_stream()
1935 azx_dev->sd_int_sta_mask = 1 << i; in azx_init_stream()
1937 azx_dev->index = i; in azx_init_stream()
1938 azx_dev->stream_tag = i + 1; in azx_init_stream()