232 	struct wm_adsp *adsp;  member
247 	struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);  in wm_adsp_fw_get()  local
249 	ucontrol->value.enumerated.item[0] = adsp[e->shift_l].fw;  in wm_adsp_fw_get()
259 	struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);  in wm_adsp_fw_put()  local
261 	if (ucontrol->value.enumerated.item[0] == adsp[e->shift_l].fw)  in wm_adsp_fw_put()
267 	if (adsp[e->shift_l].running)  in wm_adsp_fw_put()
270 	adsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];  in wm_adsp_fw_put()
379 	struct wm_adsp *adsp = ctl->adsp;  in wm_coeff_write_control()  local
384 	mem = wm_adsp_find_region(adsp, region->type);  in wm_coeff_write_control()
386 		adsp_err(adsp, "No base for region %x\n",  in wm_coeff_write_control()
398 	ret = regmap_raw_write(adsp->regmap, reg, scratch,  in wm_coeff_write_control()
401 		adsp_err(adsp, "Failed to write %zu bytes to %x: %d\n",  in wm_coeff_write_control()
406 	adsp_dbg(adsp, "Wrote %zu bytes to %x\n", ctl->len, reg);  in wm_coeff_write_control()
435 	struct wm_adsp *adsp = ctl->adsp;  in wm_coeff_read_control()  local
440 	mem = wm_adsp_find_region(adsp, region->type);  in wm_coeff_read_control()
442 		adsp_err(adsp, "No base for region %x\n",  in wm_coeff_read_control()
454 	ret = regmap_raw_read(adsp->regmap, reg, scratch, ctl->len);  in wm_coeff_read_control()
456 		adsp_err(adsp, "Failed to read %zu bytes from %x: %d\n",  in wm_coeff_read_control()
461 	adsp_dbg(adsp, "Read %zu bytes from %x\n", ctl->len, reg);  in wm_coeff_read_control()
480 	struct wm_adsp *adsp;  member
485 static int wmfw_add_ctl(struct wm_adsp *adsp, struct wm_coeff_ctl *ctl)  in wmfw_add_ctl()  argument
504 	ret = snd_soc_add_card_controls(adsp->card,  in wmfw_add_ctl()
511 	ctl->kcontrol = snd_soc_card_get_kcontrol(adsp->card,  in wmfw_add_ctl()
514 	list_add(&ctl->list, &adsp->ctl_list);  in wmfw_add_ctl()
758 static int wm_coeff_init_control_caches(struct wm_adsp *adsp)  in wm_coeff_init_control_caches()  argument
763 	list_for_each_entry(ctl, &adsp->ctl_list, list) {  in wm_coeff_init_control_caches()
776 static int wm_coeff_sync_controls(struct wm_adsp *adsp)  in wm_coeff_sync_controls()  argument
781 	list_for_each_entry(ctl, &adsp->ctl_list, list) {  in wm_coeff_sync_controls()
802 	wmfw_add_ctl(ctl_work->adsp, ctl_work->ctl);  in wm_adsp_ctl_work()
868 	ctl->adsp = dsp;  in wm_adsp_create_control()
883 	ctl_work->adsp = dsp;  in wm_adsp_create_control()
1389 int wm_adsp1_init(struct wm_adsp *adsp)  in wm_adsp1_init()  argument
1391 	INIT_LIST_HEAD(&adsp->alg_regions);  in wm_adsp1_init()
1736 int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)  in wm_adsp2_init()  argument
1744 	ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,  in wm_adsp2_init()
1747 		adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);  in wm_adsp2_init()
1751 	INIT_LIST_HEAD(&adsp->alg_regions);  in wm_adsp2_init()
1752 	INIT_LIST_HEAD(&adsp->ctl_list);  in wm_adsp2_init()
1753 	INIT_WORK(&adsp->boot_work, wm_adsp2_boot_work);  in wm_adsp2_init()
1756 		adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");  in wm_adsp2_init()
1757 		if (IS_ERR(adsp->dvfs)) {  in wm_adsp2_init()
1758 			ret = PTR_ERR(adsp->dvfs);  in wm_adsp2_init()
1759 			adsp_err(adsp, "Failed to get DCVDD: %d\n", ret);  in wm_adsp2_init()
1763 		ret = regulator_enable(adsp->dvfs);  in wm_adsp2_init()
1765 			adsp_err(adsp, "Failed to enable DCVDD: %d\n", ret);  in wm_adsp2_init()
1769 		ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);  in wm_adsp2_init()
1771 			adsp_err(adsp, "Failed to initialise DVFS: %d\n", ret);  in wm_adsp2_init()
1775 		ret = regulator_disable(adsp->dvfs);  in wm_adsp2_init()
1777 			adsp_err(adsp, "Failed to disable DCVDD: %d\n", ret);  in wm_adsp2_init()