Lines Matching refs:to

23 more modifiers. Modifiers allow the user to restrict the events to be
33  D - pin the event to the PMU
40  2 - SAMPLE_IP requested to have 0 skid
44 which supports up to precise-level 2.
46 On AMD systems it is implemented using IBS (up to precise-level 2).
48 clocks not halted) and 0xC1 (micro-ops retired). Both events map to
52 Sampling). Examples to use IBS:
81                             delivered by loop stream detector  invert to count
89 You should refer to the processor specific documentation for getting these
99 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
101 . 'sw' or 'software' to list software events such as context switches, etc.
103 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
105 . 'tracepoint' to list all tracepoint events, alternatively use
106   'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
109 . 'pmu' to print the kernel supplied PMU events.
111 . If none of the above is matched, it will apply the supplied glob to all