1 /* 2 comedi/drivers/amcc_s5933.h 3 4 Stuff for AMCC S5933 PCI Controller 5 6 Author: Michal Dobes <dobes@tesnet.cz> 7 8 Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver 9 made by Andrea Cisternino <acister@pcape1.pi.infn.it> 10 and as result of espionage from MITE code made by David A. Schleef. 11 Thanks to AMCC for their on-line documentation and bus master DMA 12 example. 13 */ 14 15 #ifndef _AMCC_S5933_H_ 16 #define _AMCC_S5933_H_ 17 18 /****************************************************************************/ 19 /* AMCC Operation Register Offsets - PCI */ 20 /****************************************************************************/ 21 22 #define AMCC_OP_REG_OMB1 0x00 23 #define AMCC_OP_REG_OMB2 0x04 24 #define AMCC_OP_REG_OMB3 0x08 25 #define AMCC_OP_REG_OMB4 0x0c 26 #define AMCC_OP_REG_IMB1 0x10 27 #define AMCC_OP_REG_IMB2 0x14 28 #define AMCC_OP_REG_IMB3 0x18 29 #define AMCC_OP_REG_IMB4 0x1c 30 #define AMCC_OP_REG_FIFO 0x20 31 #define AMCC_OP_REG_MWAR 0x24 32 #define AMCC_OP_REG_MWTC 0x28 33 #define AMCC_OP_REG_MRAR 0x2c 34 #define AMCC_OP_REG_MRTC 0x30 35 #define AMCC_OP_REG_MBEF 0x34 36 #define AMCC_OP_REG_INTCSR 0x38 37 #define AMCC_OP_REG_INTCSR_SRC (AMCC_OP_REG_INTCSR + 2) /* INT source */ 38 #define AMCC_OP_REG_INTCSR_FEC (AMCC_OP_REG_INTCSR + 3) /* FIFO ctrl */ 39 #define AMCC_OP_REG_MCSR 0x3c 40 #define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2) /* Data in byte 2 */ 41 #define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3) /* Command in byte 3 */ 42 43 #define AMCC_FIFO_DEPTH_DWORD 8 44 #define AMCC_FIFO_DEPTH_BYTES (8 * sizeof(u32)) 45 46 /****************************************************************************/ 47 /* AMCC - PCI Interrupt Control/Status Register */ 48 /****************************************************************************/ 49 #define INTCSR_OUTBOX_BYTE(x) ((x) & 0x3) 50 #define INTCSR_OUTBOX_SELECT(x) (((x) & 0x3) << 2) 51 #define INTCSR_OUTBOX_EMPTY_INT 0x10 /* enable outbox empty interrupt */ 52 #define INTCSR_INBOX_BYTE(x) (((x) & 0x3) << 8) 53 #define INTCSR_INBOX_SELECT(x) (((x) & 0x3) << 10) 54 #define INTCSR_INBOX_FULL_INT 0x1000 /* enable inbox full interrupt */ 55 /* read, or write clear inbox full interrupt */ 56 #define INTCSR_INBOX_INTR_STATUS 0x20000 57 /* read only, interrupt asserted */ 58 #define INTCSR_INTR_ASSERTED 0x800000 59 60 /****************************************************************************/ 61 /* AMCC - PCI non-volatile ram command register (byte 3 of master control/status register) */ 62 /****************************************************************************/ 63 #define MCSR_NV_LOAD_LOW_ADDR 0x0 64 #define MCSR_NV_LOAD_HIGH_ADDR 0x20 65 #define MCSR_NV_WRITE 0x40 66 #define MCSR_NV_READ 0x60 67 #define MCSR_NV_MASK 0x60 68 #define MCSR_NV_ENABLE 0x80 69 #define MCSR_NV_BUSY MCSR_NV_ENABLE 70 71 /****************************************************************************/ 72 /* AMCC Operation Registers Size - PCI */ 73 /****************************************************************************/ 74 75 #define AMCC_OP_REG_SIZE 64 /* in bytes */ 76 77 /****************************************************************************/ 78 /* AMCC Operation Register Offsets - Add-on */ 79 /****************************************************************************/ 80 81 #define AMCC_OP_REG_AIMB1 0x00 82 #define AMCC_OP_REG_AIMB2 0x04 83 #define AMCC_OP_REG_AIMB3 0x08 84 #define AMCC_OP_REG_AIMB4 0x0c 85 #define AMCC_OP_REG_AOMB1 0x10 86 #define AMCC_OP_REG_AOMB2 0x14 87 #define AMCC_OP_REG_AOMB3 0x18 88 #define AMCC_OP_REG_AOMB4 0x1c 89 #define AMCC_OP_REG_AFIFO 0x20 90 #define AMCC_OP_REG_AMWAR 0x24 91 #define AMCC_OP_REG_APTA 0x28 92 #define AMCC_OP_REG_APTD 0x2c 93 #define AMCC_OP_REG_AMRAR 0x30 94 #define AMCC_OP_REG_AMBEF 0x34 95 #define AMCC_OP_REG_AINT 0x38 96 #define AMCC_OP_REG_AGCSTS 0x3c 97 #define AMCC_OP_REG_AMWTC 0x58 98 #define AMCC_OP_REG_AMRTC 0x5c 99 100 /****************************************************************************/ 101 /* AMCC - Add-on General Control/Status Register */ 102 /****************************************************************************/ 103 104 #define AGCSTS_CONTROL_MASK 0xfffff000 105 #define AGCSTS_NV_ACC_MASK 0xe0000000 106 #define AGCSTS_RESET_MASK 0x0e000000 107 #define AGCSTS_NV_DA_MASK 0x00ff0000 108 #define AGCSTS_BIST_MASK 0x0000f000 109 #define AGCSTS_STATUS_MASK 0x000000ff 110 #define AGCSTS_TCZERO_MASK 0x000000c0 111 #define AGCSTS_FIFO_ST_MASK 0x0000003f 112 113 #define AGCSTS_RESET_MBFLAGS 0x08000000 114 #define AGCSTS_RESET_P2A_FIFO 0x04000000 115 #define AGCSTS_RESET_A2P_FIFO 0x02000000 116 #define AGCSTS_RESET_FIFOS (AGCSTS_RESET_A2P_FIFO | AGCSTS_RESET_P2A_FIFO) 117 118 #define AGCSTS_A2P_TCOUNT 0x00000080 119 #define AGCSTS_P2A_TCOUNT 0x00000040 120 121 #define AGCSTS_FS_P2A_EMPTY 0x00000020 122 #define AGCSTS_FS_P2A_HALF 0x00000010 123 #define AGCSTS_FS_P2A_FULL 0x00000008 124 125 #define AGCSTS_FS_A2P_EMPTY 0x00000004 126 #define AGCSTS_FS_A2P_HALF 0x00000002 127 #define AGCSTS_FS_A2P_FULL 0x00000001 128 129 /****************************************************************************/ 130 /* AMCC - Add-on Interrupt Control/Status Register */ 131 /****************************************************************************/ 132 133 #define AINT_INT_MASK 0x00ff0000 134 #define AINT_SEL_MASK 0x0000ffff 135 #define AINT_IS_ENSEL_MASK 0x00001f1f 136 137 #define AINT_INT_ASSERTED 0x00800000 138 #define AINT_BM_ERROR 0x00200000 139 #define AINT_BIST_INT 0x00100000 140 141 #define AINT_RT_COMPLETE 0x00080000 142 #define AINT_WT_COMPLETE 0x00040000 143 144 #define AINT_OUT_MB_INT 0x00020000 145 #define AINT_IN_MB_INT 0x00010000 146 147 #define AINT_READ_COMPL 0x00008000 148 #define AINT_WRITE_COMPL 0x00004000 149 150 #define AINT_OMB_ENABLE 0x00001000 151 #define AINT_OMB_SELECT 0x00000c00 152 #define AINT_OMB_BYTE 0x00000300 153 154 #define AINT_IMB_ENABLE 0x00000010 155 #define AINT_IMB_SELECT 0x0000000c 156 #define AINT_IMB_BYTE 0x00000003 157 158 /* these are bits from various different registers, needs cleanup XXX */ 159 /* Enable Bus Mastering */ 160 #define EN_A2P_TRANSFERS 0x00000400 161 /* FIFO Flag Reset */ 162 #define RESET_A2P_FLAGS 0x04000000L 163 /* FIFO Relative Priority */ 164 #define A2P_HI_PRIORITY 0x00000100L 165 /* Identify Interrupt Sources */ 166 #define ANY_S593X_INT 0x00800000L 167 #define READ_TC_INT 0x00080000L 168 #define WRITE_TC_INT 0x00040000L 169 #define IN_MB_INT 0x00020000L 170 #define MASTER_ABORT_INT 0x00100000L 171 #define TARGET_ABORT_INT 0x00200000L 172 #define BUS_MASTER_INT 0x00200000L 173 174 #endif 175