1 /*
2 * arch/arm/mach-at91/include/mach/cpu.h
3 *
4 * Copyright (C) 2006 SAN People
5 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14 #ifndef __MACH_CPU_H__
15 #define __MACH_CPU_H__
16
17 #define ARCH_ID_AT91RM9200 0x09290780
18 #define ARCH_ID_AT91SAM9260 0x019803a0
19 #define ARCH_ID_AT91SAM9261 0x019703a0
20 #define ARCH_ID_AT91SAM9263 0x019607a0
21 #define ARCH_ID_AT91SAM9G10 0x019903a0
22 #define ARCH_ID_AT91SAM9G20 0x019905a0
23 #define ARCH_ID_AT91SAM9RL64 0x019b03a0
24 #define ARCH_ID_AT91SAM9G45 0x819b05a0
25 #define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
26 #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
27 #define ARCH_ID_AT91SAM9X5 0x819a05a0
28 #define ARCH_ID_AT91SAM9N12 0x819a07a0
29
30 #define ARCH_ID_AT91SAM9XE128 0x329973a0
31 #define ARCH_ID_AT91SAM9XE256 0x329a93a0
32 #define ARCH_ID_AT91SAM9XE512 0x329aa3a0
33
34 #define ARCH_ID_AT91M40800 0x14080044
35 #define ARCH_ID_AT91R40807 0x44080746
36 #define ARCH_ID_AT91M40807 0x14080745
37 #define ARCH_ID_AT91R40008 0x44000840
38
39 #define ARCH_ID_SAMA5 0x8A5C07C0
40
41 #define ARCH_EXID_AT91SAM9M11 0x00000001
42 #define ARCH_EXID_AT91SAM9M10 0x00000002
43 #define ARCH_EXID_AT91SAM9G46 0x00000003
44 #define ARCH_EXID_AT91SAM9G45 0x00000004
45
46 #define ARCH_EXID_AT91SAM9G15 0x00000000
47 #define ARCH_EXID_AT91SAM9G35 0x00000001
48 #define ARCH_EXID_AT91SAM9X35 0x00000002
49 #define ARCH_EXID_AT91SAM9G25 0x00000003
50 #define ARCH_EXID_AT91SAM9X25 0x00000004
51
52 #define ARCH_EXID_SAMA5D3 0x00004300
53 #define ARCH_EXID_SAMA5D31 0x00444300
54 #define ARCH_EXID_SAMA5D33 0x00414300
55 #define ARCH_EXID_SAMA5D34 0x00414301
56 #define ARCH_EXID_SAMA5D35 0x00584300
57 #define ARCH_EXID_SAMA5D36 0x00004301
58
59 #define ARCH_EXID_SAMA5D4 0x00000007
60 #define ARCH_EXID_SAMA5D41 0x00000001
61 #define ARCH_EXID_SAMA5D42 0x00000002
62 #define ARCH_EXID_SAMA5D43 0x00000003
63 #define ARCH_EXID_SAMA5D44 0x00000004
64
65 #define ARCH_FAMILY_AT91X92 0x09200000
66 #define ARCH_FAMILY_AT91SAM9 0x01900000
67 #define ARCH_FAMILY_AT91SAM9XE 0x02900000
68
69 /* RM9200 type */
70 #define ARCH_REVISON_9200_BGA (0 << 0)
71 #define ARCH_REVISON_9200_PQFP (1 << 0)
72
73 #ifndef __ASSEMBLY__
74 enum at91_soc_type {
75 /* 920T */
76 AT91_SOC_RM9200,
77
78 /* SAM92xx */
79 AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
80
81 /* SAM9Gxx */
82 AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
83
84 /* SAM9RL */
85 AT91_SOC_SAM9RL,
86
87 /* SAM9X5 */
88 AT91_SOC_SAM9X5,
89
90 /* SAM9N12 */
91 AT91_SOC_SAM9N12,
92
93 /* SAMA5D3 */
94 AT91_SOC_SAMA5D3,
95
96 /* SAMA5D4 */
97 AT91_SOC_SAMA5D4,
98
99 /* Unknown type */
100 AT91_SOC_UNKNOWN,
101 };
102
103 enum at91_soc_subtype {
104 /* RM9200 */
105 AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
106
107 /* SAM9260 */
108 AT91_SOC_SAM9XE,
109
110 /* SAM9G45 */
111 AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
112
113 /* SAM9X5 */
114 AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
115 AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
116
117 /* SAMA5D3 */
118 AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
119 AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
120
121 /* SAMA5D4 */
122 AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
123 AT91_SOC_SAMA5D44,
124
125 /* No subtype for this SoC */
126 AT91_SOC_SUBTYPE_NONE,
127
128 /* Unknown subtype */
129 AT91_SOC_SUBTYPE_UNKNOWN,
130 };
131
132 struct at91_socinfo {
133 unsigned int type, subtype;
134 unsigned int cidr, exid;
135 };
136
137 extern struct at91_socinfo at91_soc_initdata;
138 const char *at91_get_soc_type(struct at91_socinfo *c);
139 const char *at91_get_soc_subtype(struct at91_socinfo *c);
140
at91_soc_is_detected(void)141 static inline int at91_soc_is_detected(void)
142 {
143 return at91_soc_initdata.type != AT91_SOC_UNKNOWN;
144 }
145
146 #ifdef CONFIG_SOC_AT91RM9200
147 #define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200)
148 #define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
149 #define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
150 #else
151 #define cpu_is_at91rm9200() (0)
152 #define cpu_is_at91rm9200_bga() (0)
153 #define cpu_is_at91rm9200_pqfp() (0)
154 #endif
155
156 #ifdef CONFIG_SOC_AT91SAM9260
157 #define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
158 #define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
159 #define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
160 #else
161 #define cpu_is_at91sam9xe() (0)
162 #define cpu_is_at91sam9260() (0)
163 #define cpu_is_at91sam9g20() (0)
164 #endif
165
166 #ifdef CONFIG_SOC_AT91SAM9261
167 #define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
168 #define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
169 #else
170 #define cpu_is_at91sam9261() (0)
171 #define cpu_is_at91sam9g10() (0)
172 #endif
173
174 #ifdef CONFIG_SOC_AT91SAM9263
175 #define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
176 #else
177 #define cpu_is_at91sam9263() (0)
178 #endif
179
180 #ifdef CONFIG_SOC_AT91SAM9RL
181 #define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
182 #else
183 #define cpu_is_at91sam9rl() (0)
184 #endif
185
186 #ifdef CONFIG_SOC_AT91SAM9G45
187 #define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
188 #define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
189 #define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
190 #define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
191 #define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
192 #else
193 #define cpu_is_at91sam9g45() (0)
194 #define cpu_is_at91sam9g45es() (0)
195 #define cpu_is_at91sam9m10() (0)
196 #define cpu_is_at91sam9g46() (0)
197 #define cpu_is_at91sam9m11() (0)
198 #endif
199
200 #ifdef CONFIG_SOC_AT91SAM9X5
201 #define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
202 #define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
203 #define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
204 #define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
205 #define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
206 #define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
207 #else
208 #define cpu_is_at91sam9x5() (0)
209 #define cpu_is_at91sam9g15() (0)
210 #define cpu_is_at91sam9g35() (0)
211 #define cpu_is_at91sam9x35() (0)
212 #define cpu_is_at91sam9g25() (0)
213 #define cpu_is_at91sam9x25() (0)
214 #endif
215
216 #ifdef CONFIG_SOC_AT91SAM9N12
217 #define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
218 #else
219 #define cpu_is_at91sam9n12() (0)
220 #endif
221
222 #ifdef CONFIG_SOC_SAMA5D3
223 #define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
224 #else
225 #define cpu_is_sama5d3() (0)
226 #endif
227
228 #ifdef CONFIG_SOC_SAMA5D4
229 #define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
230 #else
231 #define cpu_is_sama5d4() (0)
232 #endif
233
234 /*
235 * Since this is ARM, we will never run on any AVR32 CPU. But these
236 * definitions may reduce clutter in common drivers.
237 */
238 #define cpu_is_at32ap7000() (0)
239 #endif /* __ASSEMBLY__ */
240
241 #endif /* __MACH_CPU_H__ */
242